{"title":"通过晶圆互连技术实现先进的电子器件","authors":"M. de Samber, T. Nellissen, E. van Grunsven","doi":"10.1109/EPTC.2004.1396566","DOIUrl":null,"url":null,"abstract":"There is a need for miniaturizing electronic components such as ICs and modules that are used in portable devices like cellular phones and PDAs. Miniaturization not only results in a reduced foot print of the components on the printed board but it can also have a positive effect on the device performance. The ultimate miniaturization is reached when packaging the component into a chip size package (CSP). To enable this, the bonding pads of ICs can be rerouted into, e.g., a ball grid array (BGA) configuration. For devices such as vertical discrete components and stacked dies planar rerouting is not sufficient. Introducing so-called through wafer interconnect enables addressing the back side and so these devices can be converted into CSPs. Although through wafer interconnect requires rather complicated technologies, wafer level processing (resulting in simultaneous fabrication of large number of packages) limits the additional packaging cost.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Through wafer interconnection technologies for advanced electronic devices\",\"authors\":\"M. de Samber, T. Nellissen, E. van Grunsven\",\"doi\":\"10.1109/EPTC.2004.1396566\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"There is a need for miniaturizing electronic components such as ICs and modules that are used in portable devices like cellular phones and PDAs. Miniaturization not only results in a reduced foot print of the components on the printed board but it can also have a positive effect on the device performance. The ultimate miniaturization is reached when packaging the component into a chip size package (CSP). To enable this, the bonding pads of ICs can be rerouted into, e.g., a ball grid array (BGA) configuration. For devices such as vertical discrete components and stacked dies planar rerouting is not sufficient. Introducing so-called through wafer interconnect enables addressing the back side and so these devices can be converted into CSPs. Although through wafer interconnect requires rather complicated technologies, wafer level processing (resulting in simultaneous fabrication of large number of packages) limits the additional packaging cost.\",\"PeriodicalId\":370907,\"journal\":{\"name\":\"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPTC.2004.1396566\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC.2004.1396566","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Through wafer interconnection technologies for advanced electronic devices
There is a need for miniaturizing electronic components such as ICs and modules that are used in portable devices like cellular phones and PDAs. Miniaturization not only results in a reduced foot print of the components on the printed board but it can also have a positive effect on the device performance. The ultimate miniaturization is reached when packaging the component into a chip size package (CSP). To enable this, the bonding pads of ICs can be rerouted into, e.g., a ball grid array (BGA) configuration. For devices such as vertical discrete components and stacked dies planar rerouting is not sufficient. Introducing so-called through wafer interconnect enables addressing the back side and so these devices can be converted into CSPs. Although through wafer interconnect requires rather complicated technologies, wafer level processing (resulting in simultaneous fabrication of large number of packages) limits the additional packaging cost.