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Proceedings of 1993 IEEE International SOI Conference最新文献

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High-performance CMOS fabricated on ultrathin BESOI with sub-10 nm ttv 在超薄BESOI上制造的高性能CMOS具有低于10 nm的ttv
Proceedings of 1993 IEEE International SOI Conference Pub Date : 1993-10-05 DOI: 10.1109/SOI.1993.344562
S. S. Iyer, M. Tejwani, P. Pitner, T. Sedgwick, G. Shahidi
{"title":"High-performance CMOS fabricated on ultrathin BESOI with sub-10 nm ttv","authors":"S. S. Iyer, M. Tejwani, P. Pitner, T. Sedgwick, G. Shahidi","doi":"10.1109/SOI.1993.344562","DOIUrl":"https://doi.org/10.1109/SOI.1993.344562","url":null,"abstract":"Ultra thin Bond and Etch-back Silicon On Insulator (BESOI) in the thickness range of 75 to 100 nn offers the potential for performance enhancement in both CMOS and BiCMOS technology. To be useful, however, a very low total thickness variation (ttv) is desirable, typically below 10 nm. SIMOX can obtain high uniformity, but has high residual defect densities. Recently, a plasma-based thinning process has been able to demonstrate impressive results in thinning conventional bonded SOI wafers to ultra thin high ttv dimensions.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123696145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Enhanced chemical etching and optical observation: a quality analysis technique for industrial SIMOX production 强化化学蚀刻和光学观察:工业SIMOX生产的质量分析技术
Proceedings of 1993 IEEE International SOI Conference Pub Date : 1993-10-05 DOI: 10.1109/SOI.1993.344601
A. García, B. Aspar, J. Margail, C. Pudda
{"title":"Enhanced chemical etching and optical observation: a quality analysis technique for industrial SIMOX production","authors":"A. García, B. Aspar, J. Margail, C. Pudda","doi":"10.1109/SOI.1993.344601","DOIUrl":"https://doi.org/10.1109/SOI.1993.344601","url":null,"abstract":"SIMOX is a well developed process for producing SOI materials. However, for some applications the top silicon layer still needs crystalline quality improvements. At present the density of threading dislocations on typical SIMOX materials (1.8x10/sup 18/O/sup +/cm/sup -2/) is about 10/sup 5/cm/sup -2/ for single implantation and about 10/sup 4/cm/sup -2/ for multi-implantations. Due to the very small thickness of the top silicon layer a two step etching procedure using SECCO etching and bright field optical observations has been used to determine the dislocation density. A four step procedure which allows the transfer of the dislocation etch pits into the bulk was developed to increase the contrast between dislocation etch pits and the substrate. In this work, we describe an optimized enhanced chemical etching process. It allows etch pit observations using an optical microscope and automatic counting by the use of image processing software. This technique can be used for quality analysis and is \"operator free\".<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116838638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Formation of oxidation induced stacking sacrificial thinning of SIMOX materials SIMOX材料氧化诱导堆积牺牲减薄的形成
Proceedings of 1993 IEEE International SOI Conference Pub Date : 1993-10-05 DOI: 10.1109/SOI.1993.344595
L. Giles, A. Nejim, C. Marsh, P. Hemment, G. Booker
{"title":"Formation of oxidation induced stacking sacrificial thinning of SIMOX materials","authors":"L. Giles, A. Nejim, C. Marsh, P. Hemment, G. Booker","doi":"10.1109/SOI.1993.344595","DOIUrl":"https://doi.org/10.1109/SOI.1993.344595","url":null,"abstract":"Sacrificial thermal oxidation of standard SIMOX is currently the main route to form ultra thin film SIMOX structures. During the oxidation process self interstitials are injected into the silicon overlayer and these point defects can lead to the growth of secondary defects, in particular oxidation induced stacking faults (OISF). The formation of these OISF is influenced by the presence of stacking fault tetrahedra (SFT) in the silicon overlayer. In this paper we investigate the formation of OISF using transmission electron microscopy (TEM) and a recently developed chemical defect etchant. We propose a model which describes the evolution of OISF from the existing SFT.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"558 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114869808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Behavior of contact-silicided TFSOI gate-structures 接触硅化TFSOI栅极结构的性能
Proceedings of 1993 IEEE International SOI Conference Pub Date : 1993-10-05 DOI: 10.1109/SOI.1993.344579
J. Foerstner, J. Jones, M. Huang, B. Hwang, M. Racanelli, J. Tsao, N. Theodore
{"title":"Behavior of contact-silicided TFSOI gate-structures","authors":"J. Foerstner, J. Jones, M. Huang, B. Hwang, M. Racanelli, J. Tsao, N. Theodore","doi":"10.1109/SOI.1993.344579","DOIUrl":"https://doi.org/10.1109/SOI.1993.344579","url":null,"abstract":"As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of Thin-Film Silicon-On-Insulator (TFSOI) substrates for device fabrication is being explored in order to reduce power consumption and increase performance. SIMOX (Silicon separation by Implanted OXygen) and BESOI( Bond and Etch back Silicon On Insulator) can be used for device fabrication at this time, however the subject of this study will be CMOS device structures built on SIMOX only. Fabrication of modern MOSFET's requires formation of a silicide in both the poly gate and mono-silicon Source/Drain regions. In our case the contact silicide under investigation is a TiSi/sub 2/ layer followed by Al(Cu) metal interconnect lines. TiSi/sub 2/ has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121626240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
An analytical back gate bias dependent threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices sige通道超薄SOI PMOS器件的解析后门偏置阈值电压模型
Proceedings of 1993 IEEE International SOI Conference Pub Date : 1993-10-05 DOI: 10.1109/SOI.1993.344577
J. Kuo, M. Tang, J. Sim
{"title":"An analytical back gate bias dependent threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices","authors":"J. Kuo, M. Tang, J. Sim","doi":"10.1109/SOI.1993.344577","DOIUrl":"https://doi.org/10.1109/SOI.1993.344577","url":null,"abstract":"This paper reports an analytical threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115104494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An AFM study of surface morphology of commercial 6" SOI wafers 6" SOI晶圆表面形貌的AFM研究
Proceedings of 1993 IEEE International SOI Conference Pub Date : 1993-10-05 DOI: 10.1109/SOI.1993.344548
T. Neal, P.C. Karulkar
{"title":"An AFM study of surface morphology of commercial 6\" SOI wafers","authors":"T. Neal, P.C. Karulkar","doi":"10.1109/SOI.1993.344548","DOIUrl":"https://doi.org/10.1109/SOI.1993.344548","url":null,"abstract":"Work reported in this paper involved an extensive Atomic Force Microscopic investigation of the surface quality of 6\" SIMOX SOI wafers without any epitaxy in conjunction with a study of reliability of 19 nm or 9 nm thick gate oxide. The results illustrate that AFM studies will allow rapid development of high quality SOI substrates and that AFM, when used as a quality control tool, will assure supply of quality substrates.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123250726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Annealing characteristics of radiation induced leakage in SOS MOSFETs SOS mosfet辐射致漏的退火特性
Proceedings of 1993 IEEE International SOI Conference Pub Date : 1993-10-05 DOI: 10.1109/SOI.1993.344580
E. Y. Chao, C. Hu, S. Wu, G. Li, P. Liu, J. White, R. Kjar
{"title":"Annealing characteristics of radiation induced leakage in SOS MOSFETs","authors":"E. Y. Chao, C. Hu, S. Wu, G. Li, P. Liu, J. White, R. Kjar","doi":"10.1109/SOI.1993.344580","DOIUrl":"https://doi.org/10.1109/SOI.1993.344580","url":null,"abstract":"Recently, material procurement specifications for controlling and minimizing radiation induced leakage of integrated circuits in silicon-on-sapphire have been explored. It was demonstrated in some optimized SOS material fabrication conditions that a significant reduction in radiation induced leakage in SOS CMOS devices and circuits can be achieved at the price of somewhat reduced channel mobility and increased pre-radiation leakage levels. However, the understanding of reduction mechanisms in the radiation induced leakage is still lacking. In order to gain understanding of this phenomenon, the annealing behavior of the radiation induced leakage in SOS with new procurement specifications is investigated in this work. Based on the annealing results, a potential rad-hard method of low-temperature short-cycle annealing is proposed to cure radiation induced damage for further radiation hardening in space electronics applications.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"65 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120896256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Photoluminescence and photoreflectance scanning of silicon-on-insulator materials 绝缘体上硅材料的光致发光和光反射扫描
Proceedings of 1993 IEEE International SOI Conference Pub Date : 1993-10-05 DOI: 10.1109/SOI.1993.344607
H. Hovel
{"title":"Photoluminescence and photoreflectance scanning of silicon-on-insulator materials","authors":"H. Hovel","doi":"10.1109/SOI.1993.344607","DOIUrl":"https://doi.org/10.1109/SOI.1993.344607","url":null,"abstract":"Photoluminescence (PL) and photoreflectance (PR) intensity maps of silicon-on-insulator (SOI) wafers tend to reveal much more than bare silicon. They are often rich in features due to both reflectance variations arising from the optical properties of the multi-layer stack, and to electrical variations across the wafers. PL scanning of these materials reveals many qualitative features useful in tracking uniformity across the wafer and repeatability between wafers from different fabrication runs.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125823826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Room temperature observation of velocity overshoot in silicon inversion layers 硅反转层中速度超调的室温观测
Proceedings of 1993 IEEE International SOI Conference Pub Date : 1993-10-05 DOI: 10.1109/SOI.1993.344569
F. Assaderaghi, P. Ko, C. Hu
{"title":"Room temperature observation of velocity overshoot in silicon inversion layers","authors":"F. Assaderaghi, P. Ko, C. Hu","doi":"10.1109/SOI.1993.344569","DOIUrl":"https://doi.org/10.1109/SOI.1993.344569","url":null,"abstract":"As MOS transistor dimensions shrink to deep sub-micron regime, the non-local effects are expected to become more prominent. Perhaps the most important of these non-local effects is velocity overshoot, which can be beneficial to device performance by improving current drive and transconductance. Here, for the first time, we report direct observation of velocity overshoot using a special test structure. The first indication of velocity overshoot is seen at channel length of 0.22 /spl mu/m, while at L/sub eff/=0.12 /spl mu/m drift velocity values up to 40% higher than the long channel value are measured. The SOI NMOSFETs used in the study are built on SIMOX wafers with channel lengths from 0.12 /spl mu/m to 0.6 /spl mu/m.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133341253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Recess channel structure for reducing source/drain series resistance in ultra-thin SOI MOSFETs 用于降低超薄SOI mosfet源漏串联电阻的凹槽沟道结构
Proceedings of 1993 IEEE International SOI Conference Pub Date : 1993-10-05 DOI: 10.1109/SOI.1993.344549
M. Chan, F. Assaderaghi, S. A. Parke, S. S. Yuen, C. Hu, P. Ko
{"title":"Recess channel structure for reducing source/drain series resistance in ultra-thin SOI MOSFETs","authors":"M. Chan, F. Assaderaghi, S. A. Parke, S. S. Yuen, C. Hu, P. Ko","doi":"10.1109/SOI.1993.344549","DOIUrl":"https://doi.org/10.1109/SOI.1993.344549","url":null,"abstract":"A new Recess-Channel technology has been developed which significantly reduces the source/drain series resistance. This technology is potentially very useful for ultra-thin-film fully depleted SOI MOSFET fabrication with arbitrary silicon film thickness. Silicide technology may also be used in conjunction with the Recess-Channel technique to further reduce the source/drain series resistance and increase the current drive.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128849255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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