B. Hwang, J. Tsao, M. Racanelli, M. Huang, J. Foerstner, T. Wetteroth, Ik-Sung Lim
{"title":"Design and manufacturing considerations of a 0.5 /spl mu/m CMOS technology on TFSOI","authors":"B. Hwang, J. Tsao, M. Racanelli, M. Huang, J. Foerstner, T. Wetteroth, Ik-Sung Lim","doi":"10.1109/SOI.1993.344565","DOIUrl":"https://doi.org/10.1109/SOI.1993.344565","url":null,"abstract":"While thin film SOI (TFSOI) advantages over bulk technology have been reported over the past many years, the TFSOI commodity products are yet to be introduced. Applications of SOI remain in the thick film rad-hard oriented niche market. Theoretical study and silicon implementation of SOI physics and a cost model have for the most part supported the advantages of TFSOI. This paper discusses considerations for the SOI manufacturing feasibility, and the implication to the TFSOI product introduction. The emphasis is placed on the 0.5 /spl mu/m level since this is the state-of-the-art geometry for production of bulk CMOS. Also the huge capital expense for a fabrication line at 0.5 /spl mu/m and beyond will inevitably prolong the technology lifetime and call for value added technology. TFSOI technology at 0.5 /spl mu/m fits into the above category.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132961996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Generation lifetime measurements in fully depleted enhancement and accumulation mode SOI MOSFETs","authors":"S. Sinha, A. Zaleski, D. Ioannou, F. Brady","doi":"10.1109/SOI.1993.344582","DOIUrl":"https://doi.org/10.1109/SOI.1993.344582","url":null,"abstract":"In this work we present a unified analysis for both enhancement and accumulation mode devices, by considering the temporal variation of the quasi-Fermi levels. This leads to an accurate determination of the generation volume, and to Zerbst-type expressions for the drain current transients for enhancement equation and accumulation equation mode devices.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131748183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Effects of self-heating-induced negative output conductance in SOI circuits","authors":"M. Fox, J. Brodsky","doi":"10.1109/SOI.1993.344555","DOIUrl":"https://doi.org/10.1109/SOI.1993.344555","url":null,"abstract":"Numerous authors have observed that self-heating can lead to negative output conductance in SOI MOSFETs. To date little consideration has been given to the effects of such behavior on circuit operation. This paper presents a first-order analysis of self-heating effects on circuits, and demonstrates through simulation and analysis that self-heating can cause even simple circuits to exhibit complicated nonlinear behavior. Heat-flow analysis shows that thermal resistances in contemporary SOI technologies are large enough that such effects are possible in practical circuits.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129804169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Sadana, H. Hovel, J. Freeouf, S. Chu, P. McFarland, M. Guerra
{"title":"Material development of SIMOX with a thin box","authors":"D. Sadana, H. Hovel, J. Freeouf, S. Chu, P. McFarland, M. Guerra","doi":"10.1109/SOI.1993.344610","DOIUrl":"https://doi.org/10.1109/SOI.1993.344610","url":null,"abstract":"It is well established that CMOS SOI technology provides improved device and circuit performance compared to bulk silicon. Extremely fast ring oscillators with delay time as low as 20 ps at 1.5 V and operating at room temperature have been demonstrated on SIMOX material. The standard SIMOX contains a thin SOI layer of 1800 /spl Aring/ and a buried oxide (BOX) of 3800 /spl Aring/. It appears from the simulation data that an optimum fully depleted SOI device may require a BOX of /spl lsim/2000 /spl Aring/ for two reasons: (i) to allow field lines to penetrate through the BOX and (ii) to minimize superficial Si heating. The SIMOX material development for the present investigation is therefore aimed at optimizing implant/annealing conditions which provide a thin BOX (/spl lsim/2000 /spl Aring/) and lower defects.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130965500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The effect of intrinsic body resistance on the breakdown characteristics of DBTS NFD SOI MOSFET's","authors":"Dongwoo Suh, J. Fossum","doi":"10.1109/SOI.1993.344588","DOIUrl":"https://doi.org/10.1109/SOI.1993.344588","url":null,"abstract":"The existence of non-zero body resistance (R/sub B/) in the DBTS (double-body-tied-to-source) NFD (non-fully depleted) SOI MOSFET structure leads to bipolar-induced premature breakdown, the mechanism of which is similar to the parasitic bipolar effect in the bulk MOSFET. The conditions can be misleading, however, because the holding voltage and the snapback voltage are indistinguishably referred to as the breakdown voltage, and the stated condition for breakdown, i.e., (M-1)/spl beta/=1, is independent of R/sub B/. To clarify this issue and to give physical insight regarding the efficacy of the DBTS, we analyze the breakdown characteristics and their dependence on R/sub B/, and we present simple but physical descriptions of the holding and snapback voltages. The derivations are aided and supported by simulations using SOISPICE-3, in which we have implemented a physics-based model for the NFD SOI MOSFET.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"24 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131207389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"New SOI-based applications","authors":"A. Auberton-Herve","doi":"10.1109/SOI.1993.344612","DOIUrl":"https://doi.org/10.1109/SOI.1993.344612","url":null,"abstract":"Since the end of the 80's, SOI developments in general have raised an increased interest due to the material's commercial availability. The SIMOX technique (Separation by IMplanted OXygen) was the first to provide ultra thin silicon monocrystalline film on top of silicon dioxide as an industrial product and is leading in the SOI industrial developments. The new developments in oxygen ion implantation have pushed the limit of the SIMOX technology to the thinnest insulating layer commercially available. The standard insulating layer was until today 400 nm. The new product we have developed named \"low dose product\", has a buried oxide layer as thin as 80 nm. The silicon layer on top can be adjusted down to 50 nm thereby providing the thinnest combination of SOI layers. The applications of such thin films are in the field of low voltage products. The battery operated ICs for portable systems and ULSI CMOS logic ICs with gate length below 0.2 /spl mu/m are expected to be the two major applications of this new material. The speed improvement of SOI ICs compared to standard silicon technologies is better than a factor of two for low voltage with a lower power consumption. Additional advantages of using SOI is the higher packing density and a simplified process compared to standard technologies. Other applications include: MMICs, BiCMOS, optoelectronics, and smart power.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128131097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Inversion electron effective mobility in SOI NMOSFETs","authors":"M. Sherony, L. T. Su, J. E. Chung, D. Antoniadis","doi":"10.1109/SOI.1993.344567","DOIUrl":"https://doi.org/10.1109/SOI.1993.344567","url":null,"abstract":"Due to reported advantages over bulk silicon, thin-film SOI has developed the potential of becoming a mainstream digital technology. In order to accurately model SOI device operation, it is necessary to understand further the channel electron mobility behavior. Some work has been done in characterising the electron mobility in SOI devices and an enhanced mobility effect has been reported by several authors for fully-depleted devices. In these works, the mobility was found to increase for thinner films and this mobility enhancement has been attributed to a decreased vertical electric field in the channel. For the same gate drive, (V/sub gs/-V/sub th/), the thinner fully-depleted SOI device has a reduced transverse field and thus a higher mobility. This work examines the effective mobility (/spl mu//sub eff/) as a function of a transverse effective electric field (E/sub eff/) rather than gate voltage or gate drive.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121242876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Considerations for SIMOX low voltage applications","authors":"M. Alles, W. Krull","doi":"10.1109/SOI.1993.344542","DOIUrl":"https://doi.org/10.1109/SOI.1993.344542","url":null,"abstract":"The IC industry move to low voltage presents an opportunity to which SIMOX is well suited. In particular, process simplification related to junction engineering and material cost reduction related to use of thinner buried oxide (BOX) are opportunities to enhance the serious commercialization of SIMOX for low voltage applications. This work addresses issues relevant to the application of present and next generation SIMOX materials and devices to low voltage applications. Advantages of SIMOX operation at low voltage are examined, and results of an analytical analysis of the effects of BOX thickness on associated parasitic capacitances are presented. The analysis shows that SIMOX on P-type substrates maintain the reduced capacitance advantages as the BOX is thinned.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129390807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Jerome, I. Post, T.G. Travnicek, G.M. Wodek, K.E. Huffstater, D.R. Williams
{"title":"ACUTE: a high performance analog complementary polysilicon emitter bipolar technology utilizing SOI/trench full dielectric isolation","authors":"R. Jerome, I. Post, T.G. Travnicek, G.M. Wodek, K.E. Huffstater, D.R. Williams","doi":"10.1109/SOI.1993.344573","DOIUrl":"https://doi.org/10.1109/SOI.1993.344573","url":null,"abstract":"The advantages of using full dielectric isolation, in the form of SOI substrates and trench isolation, are well known, namely the reduction of substrate parasitic currents due to high voltage, high temperature or harsh radiation environments. Moreover, high voltage analog bipolar transistors can also benefit from full dielectric isolation in terms of limiting substrate capacitance and providing the means to achieve well matched, densely packed transistors. A high voltage analog SOI/trench dielectrically isolated complementary bipolar technology is described, which achieves well matched, leakage-free high-speed transistor performance.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125383100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High speed whole wafer film thickness mapper","authors":"A. Ledger, P. Clapis","doi":"10.1109/SOI.1993.344590","DOIUrl":"https://doi.org/10.1109/SOI.1993.344590","url":null,"abstract":"An instrument for rapidly generating a thickness map of the silicon overlayer in SOI wafers has recently been developed. This instrument can view entire wafers up to 200 mm in diameter by using a high-resolution wide-field optical system and CCD camera. The output from the camera comprises a set of digitized multispectral images of the SOI wafer; these images are used to generate reflectance maps of the bonded wafer at a discrete number of wavelengths and are then used to compute the silicon thickness over the entire wafer by comparing measured spectral patterns with a pre-computed library. Pattern matching algorithms are used in conjunction with a parallel processor, yielding measurement speeds orders of magnitude faster than conventional instruments (e.g. one minute for a 64/spl times/64 array of locations). The technique simultaneously measures the buried oxide thickness, an important capability in SOI wafer fabrication. Measurement accuracy is better than /spl plusmn/2 nm with excellent repeatability.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121742588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}