Design and manufacturing considerations of a 0.5 /spl mu/m CMOS technology on TFSOI

B. Hwang, J. Tsao, M. Racanelli, M. Huang, J. Foerstner, T. Wetteroth, Ik-Sung Lim
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引用次数: 12

Abstract

While thin film SOI (TFSOI) advantages over bulk technology have been reported over the past many years, the TFSOI commodity products are yet to be introduced. Applications of SOI remain in the thick film rad-hard oriented niche market. Theoretical study and silicon implementation of SOI physics and a cost model have for the most part supported the advantages of TFSOI. This paper discusses considerations for the SOI manufacturing feasibility, and the implication to the TFSOI product introduction. The emphasis is placed on the 0.5 /spl mu/m level since this is the state-of-the-art geometry for production of bulk CMOS. Also the huge capital expense for a fabrication line at 0.5 /spl mu/m and beyond will inevitably prolong the technology lifetime and call for value added technology. TFSOI technology at 0.5 /spl mu/m fits into the above category.<>
基于TFSOI的0.5 /spl mu/m CMOS技术的设计与制造考虑
虽然薄膜SOI (TFSOI)在过去的许多年中已经报道了其相对于大宗技术的优势,但TFSOI的商品产品尚未被引入。SOI的应用仍停留在厚膜硬定向的利基市场。SOI物理和成本模型的理论研究和硅实现在很大程度上支持了TFSOI的优势。本文讨论了SOI制造可行性的考虑,以及对TFSOI产品引进的启示。重点放在0.5 /spl mu/m水平上,因为这是批量CMOS生产的最先进的几何结构。此外,0.5 /spl μ m及以上的生产线的巨额资本支出将不可避免地延长技术寿命,并要求采用增值技术。0.5 /spl mu/m的TFSOI技术就属于上述范畴。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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