{"title":"Performance issues of SOI CMOS circuits at low supply voltages","authors":"H. Abel, G. Zimmer","doi":"10.1109/SOI.1993.344572","DOIUrl":"https://doi.org/10.1109/SOI.1993.344572","url":null,"abstract":"Circuit applications working at typical battery voltages (1.35...1.55 V) promise to be an interesting market for SOI technology. Reduced extrinsic capacitances, low leakage currents, nearly ideal subthreshold slopes and improved scalability offer several advantages over conventional CMOS circuits, particularly in regard of power consumption and circuit speed In this paper we use the SPICE implementation of our charge sheet model of the thin-film SOI MOSFET to investigate quantitatively the performance of digital SOI CMOS circuits in the voltage range from 1 to 2 V. The charge sheet principle allows us to include the subthreshold range into the simulation without losing the consistency with well established strong inversion models. The calculations are based on a SIMOX process with t/sub of/=20 nm, t/sub b/=80 nm, t/sub ob/=350 nm. The threshold voltages of the n-channel and p-channel transistors are assumed to be 0.4 V and 0.5 V, respectively. Most of the model parameters for both SOI and bulk silicon MOS devices-the latter ones are described with the SPICE Level 3 MOSFET model-have been extracted from numerical device simulations.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130431360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Hovel, J. Freeouf, Kevin S. Beyer, D. Sadana, S. Chu
{"title":"Non-destructive characterization techniques for SOI substrates","authors":"H. Hovel, J. Freeouf, Kevin S. Beyer, D. Sadana, S. Chu","doi":"10.1109/SOI.1993.344602","DOIUrl":"https://doi.org/10.1109/SOI.1993.344602","url":null,"abstract":"Silicon-on-insulator (SOI) is very promising for submicron CMOS due to low parasitic capacitance, higher potential speed, and ease of isolation. The major requirements for the starting material are: 1) thin Si layers, 2) low active defect densities, 3) highly uniform layers, and 4) good crystalline and electrical quality. Since the variation in these parameters from wafer-to-wafer and run-to-run can be substantial, it is beneficial to qualify the starting wafers as much as possible before using them in circuit runs. An arsenal of characterization techniques has been developed to do this, emphasizing non-contact, non-destructive methods as much as possible. The methods discussed include: spectroscopic ellipsometry, automatic defect counting, photoluminescence scanning, and surface photovoltage response measurement.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133439480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Conduction mechanisms through SIMOX buried oxide","authors":"J. Yap, T. Maung, J. Nee, E. Simic, J. E. Chung","doi":"10.1109/SOI.1993.344604","DOIUrl":"https://doi.org/10.1109/SOI.1993.344604","url":null,"abstract":"In this study, the electric-field, time, and temperature dependence of intrinsic SIMOX buried-oxide conduction has been characterized. Asymmetry was observed between positive and negative applied gate voltage. Two primary conduction regimes have been identified for both polarities: a high-field regime that appears to be due to Fowler-Nordheim tunneling with substantial apparent barrier-height lowering at both injecting interfaces, and a low-field regime likely due to time-dependent trapping current.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114727856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CMOS/DMOS power IC technology on thin-film SOI substrates","authors":"G.M. Dolny, A. Ipri, M. Batty","doi":"10.1109/SOI.1993.344543","DOIUrl":"https://doi.org/10.1109/SOI.1993.344543","url":null,"abstract":"A power IC technology integrating low-voltage CMOS with high-voltage current, high-voltage DMOS on a thin-film SOI substrate has been successfully demonstrated. The low-voltage CMOS exhibit good electrical characteristics and the power DMOS can supply more than 3 A of current and is capable of withstanding 120 V.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131928540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Campisi, P. Thompson, M. Anc, B. Cordts, D. Ioannou
{"title":"A SiGe strain layer for gettering Fe in SIMOX","authors":"G. Campisi, P. Thompson, M. Anc, B. Cordts, D. Ioannou","doi":"10.1109/SOI.1993.344594","DOIUrl":"https://doi.org/10.1109/SOI.1993.344594","url":null,"abstract":"Device processing introduces metallic contaminants that result in a reduction of device yields and reliability as well as higher gate oxide failure rates. Fortunately, these contaminants can be removed or neutralized at gettering sites associated with bulk oxygen precipitates and backside defects formed by a doped polysilicon layer. The problem with SIMOX, on the other hand, is the gettering sites are isolated by the buried oxide and additional metals can be introduced during O/sup +/ ion implantation and high temperature annealing. Here, we describe a new gettering process; the removal of metal contaminants from SIMOX using an MBE epitaxial SiGe alloy strain layer grown on a SIMOX silicon film. A SiGe alloy, with the desired germanium concentration and layer thickness, provides a highly strained region that acts as a sink(getter) for metals. With thermal cycling metals diffuse to or are driven into the surface strain layer for later removal. To demonstrate this effect and test the SiGe gettering strain layer effectiveness in SIMOX, we introduced a source of Fe/sup 54/ by implantation which is then diffused into the strain layer with an anneal. We analyzed the resulting material using TXRS (low angle surface reflection total X-ray fluorescence analysis), SIMS (Secondary Ion Mass Spectroscopy), and DLTS (Deep Level Transient Spectroscopy) measured on backgate on n-FET.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123986740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improvement of the performances of SOI CMOS operational amplifiers by means of a gain-boosting stage","authors":"B. Gentinne, J. Colinge, P. Jespers, J. Eggermont","doi":"10.1109/SOI.1993.344545","DOIUrl":"https://doi.org/10.1109/SOI.1993.344545","url":null,"abstract":"Both measurements and simulations have shown that the use of a gain-boosting architecture increases significantly the gain of the amplifier. Up to now, we have obtained very encouraging measurement results: a DC gain of 90 dB and a transition frequency of 30 MHz on a 16 pF load. The next prototypes under fabrication should give full satisfaction and correspond to the initial specifications: a DC gain of 120 dB and a transition frequency of 60 MHz on a 16 pF load.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129972391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High performance submicron SOI/CMOS with an elevated source/drain structure","authors":"J. Hwang, E. Yee, T. Houston, G. Pollack","doi":"10.1109/SOI.1993.344563","DOIUrl":"https://doi.org/10.1109/SOI.1993.344563","url":null,"abstract":"To overcome the source/drain resistance problem associated with complete silicidation of thin SOI films, we used an elevated source/drain structure in which the channel region was thinned by local oxidation and wet etch while the source/drain region remained thick. This structure achieved source/drain resistances as small as 300 ohm-/spl mu/m for NMOS, which made possible high drive currents in deep submicron thin-film SOI/MOSFETs.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128901888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electron trapping in SIMOX with supplemental implant","authors":"R. J. Lambert, T. Bhar, H. Hughes","doi":"10.1109/SOI.1993.344587","DOIUrl":"https://doi.org/10.1109/SOI.1993.344587","url":null,"abstract":"Silicon-on-insulator (SOI) technology provides integrated circuits with several advantages over bulk silicon technology. These advantages include increased speed (due to reduced capacitance), dielectric isolation (prevents latch-up), high temperature operation, higher packing density, and enhanced performance in radiation environments. The leading SOI technology today is Separation by Implantation of Oxygen (SIMOX). The performance of devices fabricated in the silicon overlayer is highly dependent on the electrical properties of the buried oxide. A persistent problem with buried oxide materials has been the presence of large numbers of electron traps in the oxide. Several schemes have been tried in order to reduce or eliminate this effect. This study presents the results from implanting supplemental oxygen into the buried oxide. Avalanche electron injection was used to determine the density of oxide trapped charge due to electron traps in the buried oxide.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128997851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A model for double snapback phenomena in N channel SOI MOSFETs","authors":"J.S.T. Huang","doi":"10.1109/SOI.1993.344566","DOIUrl":"https://doi.org/10.1109/SOI.1993.344566","url":null,"abstract":"In the double snapback phenomenon exhibited by a N channel MOSFET, the device is observed to switch from the first to the second snapback states. The first snapback can be attributed to either an MOS or bipolar feedback mechanism. This paper proposes a physical model that is able to provide explanations for the observed dependance of second snapback on the gate voltage and the channel length.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117010756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Self-heating effects on SOI devices and implication to parameter extraction","authors":"D. Yachou, J. Gautier, C. Raynaud","doi":"10.1109/SOI.1993.344557","DOIUrl":"https://doi.org/10.1109/SOI.1993.344557","url":null,"abstract":"In SOI devices heat dissipation is limited by a buried oxide layer. The consequence is the well known Self Heating (SH) phenomenon. We have analysed in depth the corresponding thermal effects on static and dynamic modes and the implications for the device operation. In this paper the original contributions are the following: decorrelation of temperature effects on the drain current via temperature dependence of mobility and impact ionization generation rate G/sub ii/. This results in a comprehensive explanation of the output conductance attenuation with increasing gate voltage (V/sub gs/). Analysis of displacement current effects, SH and impact ionization on transient device operation. Application to device modeling: proposal of a method for the parameters extraction that takes into account the nonlinear distortion of static output characteristics due to the SH phenomenon. The self-heating analysis, in this paper, is related to a 0.8 /spl mu/m technology on SIMOX substrate developed by LETI-CEA. The devices are enhancement mode n-channel MOSFETs.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122488539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}