Behavior of contact-silicided TFSOI gate-structures

Abstract

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of Thin-Film Silicon-On-Insulator (TFSOI) substrates for device fabrication is being explored in order to reduce power consumption and increase performance. SIMOX (Silicon separation by Implanted OXygen) and BESOI( Bond and Etch back Silicon On Insulator) can be used for device fabrication at this time, however the subject of this study will be CMOS device structures built on SIMOX only. Fabrication of modern MOSFET's requires formation of a silicide in both the poly gate and mono-silicon Source/Drain regions. In our case the contact silicide under investigation is a TiSi/sub 2/ layer followed by Al(Cu) metal interconnect lines. TiSi/sub 2/ has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions.<>