{"title":"sige通道超薄SOI PMOS器件的解析后门偏置阈值电压模型","authors":"J. Kuo, M. Tang, J. Sim","doi":"10.1109/SOI.1993.344577","DOIUrl":null,"url":null,"abstract":"This paper reports an analytical threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An analytical back gate bias dependent threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices\",\"authors\":\"J. Kuo, M. Tang, J. Sim\",\"doi\":\"10.1109/SOI.1993.344577\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper reports an analytical threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide.<<ETX>>\",\"PeriodicalId\":308249,\"journal\":{\"name\":\"Proceedings of 1993 IEEE International SOI Conference\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-10-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1993 IEEE International SOI Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.1993.344577\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1993 IEEE International SOI Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.1993.344577","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An analytical back gate bias dependent threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices
This paper reports an analytical threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide.<>