M. Chan, F. Assaderaghi, S. A. Parke, S. S. Yuen, C. Hu, P. Ko
{"title":"用于降低超薄SOI mosfet源漏串联电阻的凹槽沟道结构","authors":"M. Chan, F. Assaderaghi, S. A. Parke, S. S. Yuen, C. Hu, P. Ko","doi":"10.1109/SOI.1993.344549","DOIUrl":null,"url":null,"abstract":"A new Recess-Channel technology has been developed which significantly reduces the source/drain series resistance. This technology is potentially very useful for ultra-thin-film fully depleted SOI MOSFET fabrication with arbitrary silicon film thickness. Silicide technology may also be used in conjunction with the Recess-Channel technique to further reduce the source/drain series resistance and increase the current drive.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Recess channel structure for reducing source/drain series resistance in ultra-thin SOI MOSFETs\",\"authors\":\"M. Chan, F. Assaderaghi, S. A. Parke, S. S. Yuen, C. Hu, P. Ko\",\"doi\":\"10.1109/SOI.1993.344549\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new Recess-Channel technology has been developed which significantly reduces the source/drain series resistance. This technology is potentially very useful for ultra-thin-film fully depleted SOI MOSFET fabrication with arbitrary silicon film thickness. Silicide technology may also be used in conjunction with the Recess-Channel technique to further reduce the source/drain series resistance and increase the current drive.<<ETX>>\",\"PeriodicalId\":308249,\"journal\":{\"name\":\"Proceedings of 1993 IEEE International SOI Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-10-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1993 IEEE International SOI Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.1993.344549\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1993 IEEE International SOI Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.1993.344549","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Recess channel structure for reducing source/drain series resistance in ultra-thin SOI MOSFETs
A new Recess-Channel technology has been developed which significantly reduces the source/drain series resistance. This technology is potentially very useful for ultra-thin-film fully depleted SOI MOSFET fabrication with arbitrary silicon film thickness. Silicide technology may also be used in conjunction with the Recess-Channel technique to further reduce the source/drain series resistance and increase the current drive.<>