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Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)最新文献

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Plasma treatment after interconnect metal etch for recovery of plasma charge-induced damages 互连金属蚀刻后等离子体处理修复等离子体电荷损伤
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854307
Shin Seung Park, C. Choi, Jin Woong Kim, J. Hwang
{"title":"Plasma treatment after interconnect metal etch for recovery of plasma charge-induced damages","authors":"Shin Seung Park, C. Choi, Jin Woong Kim, J. Hwang","doi":"10.1109/IITC.2000.854307","DOIUrl":"https://doi.org/10.1109/IITC.2000.854307","url":null,"abstract":"Plasma charge-induced damage has been investigated during metal interconnection in SrBi/sub 2/Ta/sub 2/O/sub 9/(SBT)-FeRAM device. The degradation of the ferroelectric characteristics, such as coercive voltage shift, was predominantly attributed to the metal etching that would inject electrons through the metal antenna and contacts. We also found that the degradation was not caused by a sputtering process in deposition of metal films or mechanical stress of patterned metal pads. To recover the plasma charge-induced damage, we suggest that a soft plasma treatment after metal plasma etching can neutralize charge-up of the electrons so that the degradation of electric properties is minimized.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133714739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Copper dual damascene interconnects with very low-k dielectrics targeting for 130 nm node 铜双大马士革互连与非常低k介电目标为130纳米节点
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854345
H. Kudo, Y. Yoshie, S. Yamaguchi, K. Watanabe, M. Ikeda, K. Kakamu, T. Hosoda, K. Ohhira, N. Santoh, N. Misawa, K. Matsuno, Y. Wakasugi, A. Hasegawa, K. Nagase, T. Suzuki
{"title":"Copper dual damascene interconnects with very low-k dielectrics targeting for 130 nm node","authors":"H. Kudo, Y. Yoshie, S. Yamaguchi, K. Watanabe, M. Ikeda, K. Kakamu, T. Hosoda, K. Ohhira, N. Santoh, N. Misawa, K. Matsuno, Y. Wakasugi, A. Hasegawa, K. Nagase, T. Suzuki","doi":"10.1109/IITC.2000.854345","DOIUrl":"https://doi.org/10.1109/IITC.2000.854345","url":null,"abstract":"It is a great concern that a so-called full low-k interlayer dielectric (ILD) structure may degrade reliability of Cu wiring due to the poor thermal conductivity of very low-k (VLK) material. An ILD structure we proposed in this work (named hybrid) are made of VLK for the trench level and SiO/sub 2/ for the via level, to meet following two requirements; reducing wiring capacitance and not decreasing thermal conductivity so much. In this work, we have presented integration of dual damascene patterning and Cu metallization for the hybrid structure.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133828909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Effect of TiCl/sub 4/ pre-treatment in PECVD-Ti process for sub-0.2 /spl mu/m metal bit line contacts PECVD-Ti工艺中TiCl/ sub4 /预处理对低于0.2 /spl mu/m金属钻头线触头的影响
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854285
S. Kang, K. Moon, H. Park, M. Lee, Gilheyun Choi, Y. Park, Sang In Lee, M. Lee
{"title":"Effect of TiCl/sub 4/ pre-treatment in PECVD-Ti process for sub-0.2 /spl mu/m metal bit line contacts","authors":"S. Kang, K. Moon, H. Park, M. Lee, Gilheyun Choi, Y. Park, Sang In Lee, M. Lee","doi":"10.1109/IITC.2000.854285","DOIUrl":"https://doi.org/10.1109/IITC.2000.854285","url":null,"abstract":"The effect of the initial steps in PECVD-Ti process is investigated for the optimization of TiSi/sub x/ formation. A remarkable difference in TiSi/sub x/ formation is observed between pre-plasma and pre-TiCl/sub 4/ treatment in which the initial steps start with H/sub 2/ gas with plasma and TiCl/sub 4/ gas without plasma. TiCl/sub 4/ pre-treatment in the PECVD-Ti process is compared with H/sub 2/ plasma pre-treatment especially for low aspect ratio contacts. PECVD-Ti films with H/sub 2/ plasma pre-treatment results in accumulation of Cl impurities at the interface between Si and TiSi/sub x/, and subsequently results in thinner TiSi/sub x/ and higher contact resistance. With the optimized TiCl/sub 4/ pretreatment, excellent electrical characteristics are obtained in sub-0.2 /spl mu/m bit line contacts.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129234517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Comparative analysis of metal and optical interconnect technology 金属与光学互连技术的比较分析
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854270
D. Jiang, B. Bhuva, D. Kerns, S. Kerns
{"title":"Comparative analysis of metal and optical interconnect technology","authors":"D. Jiang, B. Bhuva, D. Kerns, S. Kerns","doi":"10.1109/IITC.2000.854270","DOIUrl":"https://doi.org/10.1109/IITC.2000.854270","url":null,"abstract":"Barriers to industrial implementation of optical interconnects on an IC center on the balance between power requirements and speed improvements over existing metal interconnect systems. This paper focuses on such comparison based on empirically measured quantum efficiency and circuit-level projections. Multiple forms of clock distribution schemes are analyzed to show that the power requirements for optical interconnect are comparable to those of conventional metal interconnects. Implementing optical technology on long interconnect lines will improve the speed performance of ICs. The availability of such a method will allow design engineers to guide the partitioning of optical and conventional interconnects within ICs.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116161001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Multilevel test structures for metal CMP integration application to Cu/SiO/sub 2/ damascene interconnect Cu/SiO/sub / damascene互连中金属CMP集成应用的多级测试结构
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854271
M. Fayolle, P. Gayet, Y. Morand
{"title":"Multilevel test structures for metal CMP integration application to Cu/SiO/sub 2/ damascene interconnect","authors":"M. Fayolle, P. Gayet, Y. Morand","doi":"10.1109/IITC.2000.854271","DOIUrl":"https://doi.org/10.1109/IITC.2000.854271","url":null,"abstract":"This paper presents a method to evaluate the metal CMP impact on the performance of multilevel interconnect. For this purpose specific two metal level test structures have been defined, after a brief description of these structures, we present the results obtained on a Cu/SiO/sub 2/ dual damascene architecture. It is shown that the upper metal yield is drastically degraded by the underlying metal layer patterns. Therefore a two levels study is essential to integrate a metal CMP in a multilevel metallization.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114803615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The characterization of trimethylsilane based PE-CVD /spl alpha/-SiCO:H low-k films 三甲基硅烷基PE-CVD /spl α /-SiCO:H低k薄膜的表征
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854279
B.K. Wang, M.J. Loboda, G.A. Cerny, R. F. Schneider, J.A. Seifferly, T. Washer
{"title":"The characterization of trimethylsilane based PE-CVD /spl alpha/-SiCO:H low-k films","authors":"B.K. Wang, M.J. Loboda, G.A. Cerny, R. F. Schneider, J.A. Seifferly, T. Washer","doi":"10.1109/IITC.2000.854279","DOIUrl":"https://doi.org/10.1109/IITC.2000.854279","url":null,"abstract":"The trimethylsilane (3MS) based low-k /spl alpha/-SiCO:H films can be made using 3MS, He and N/sub 2/O in typical PECVD equipment. In this study, the structure, composition, and electrical characteristics of these films were evaluated with different process conditions. RBS and FTIR were evaluated to understand the composition and structure of films. The films have been characterized as-deposited and after annealing at 400/spl deg/C to see the thermal stability. 3MS low-k /spl alpha/-SiCO:H films showed low bulk film density (1.14-1.34 g/cm/sup 3/), low-k (2.6<k<3.2), low leakage current density (J<10/sup -10/ A/cm/sup 2/ at 1 MV/cm), and relatively high breakdown field (E>4 MV/cm at 1 mA/cm/sup 2/).","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121666192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Film properties and surface profile after gap fill of electrochemically deposited Cu films by DC and pulse reverse processes 直流和脉冲反相电化学沉积Cu膜的薄膜性能和表面形貌
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854319
C. Hsieh, S.W. Chou, S. Shue, C. Yu, M. Liang
{"title":"Film properties and surface profile after gap fill of electrochemically deposited Cu films by DC and pulse reverse processes","authors":"C. Hsieh, S.W. Chou, S. Shue, C. Yu, M. Liang","doi":"10.1109/IITC.2000.854319","DOIUrl":"https://doi.org/10.1109/IITC.2000.854319","url":null,"abstract":"The self-annealing and the surface reflectivity of Cu films prepared by electrochemical deposition (ECD) are obtained for the DC and pulse reverse processes. They show different behaviors for these two processes, and their behaviors can be well correlated with the grain size of the films. The mechanism of gap fill is discussed according to the surface profile after gap fill for these two processes. It is proposed that the gap filling is mainly controlled by the additive diffusion for the DC process, while it is mainly controlled by the additive adsorption for the pulse reverse process.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134166662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel via blockage model and its implications 一种新的通孔堵塞模型及其启示
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854267
Qiang Chen, J.A. Davis, P. Zarkesh-Ha, J. Meindl
{"title":"A novel via blockage model and its implications","authors":"Qiang Chen, J.A. Davis, P. Zarkesh-Ha, J. Meindl","doi":"10.1109/IITC.2000.854267","DOIUrl":"https://doi.org/10.1109/IITC.2000.854267","url":null,"abstract":"Via blockage and its impact on wirability of multi-billion transistor chips are systematically analyzed. Along with a new via distribution based on a stochastic interconnect length distribution and on optimal multilevel interconnect network architecture, a physical via blockage model exploiting channel availability is proposed and applied to analyze future multi-level interconnect networks. This model reveals that the most severe via blockage occurs on first metal level, wasting more than 10% and up to about 50% of wiring area. A new perspective on chip size limit imposed by via blockage is also projected for future chips by using the proposed model.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"268 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133944377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
RF etch pre-clean effect on PVD Al filling with low k SiLK IMD RF蚀刻预清洁对低k SiLK IMD PVD Al填充的影响
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854304
Su-Keon Lee, M. Chae, Heongsoo Kim, Taek-Gi Kim, Sibum Kim, Chung-Tae Kim, J. Hwang
{"title":"RF etch pre-clean effect on PVD Al filling with low k SiLK IMD","authors":"Su-Keon Lee, M. Chae, Heongsoo Kim, Taek-Gi Kim, Sibum Kim, Chung-Tae Kim, J. Hwang","doi":"10.1109/IITC.2000.854304","DOIUrl":"https://doi.org/10.1109/IITC.2000.854304","url":null,"abstract":"A issue related with the integration of PVD Al metallization with low k SiLK dielectrics was investigated. SiLK polymer material was severely damaged during RF etch pre-clean step which was performed to remove the AlOx layer formed on Al line in via structure. The degraded SiLK surface affected strongly the texture of Ti and Al film and then promoted the agglomeration when thin Al film was deposited on via side wall. The improvement of Al filling ability was carried out with the optimized RF etch condition.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123969387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Estimation of the signal-to-noise ratio for on-chip wireless clock signal distribution (year 2000) 片上无线时钟信号分配的信噪比估计(2000年)
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854082
D. Bravo, H. Yoon, Kihong Kim, B. Floyd, K. O
{"title":"Estimation of the signal-to-noise ratio for on-chip wireless clock signal distribution (year 2000)","authors":"D. Bravo, H. Yoon, Kihong Kim, B. Floyd, K. O","doi":"10.1109/IITC.2000.854082","DOIUrl":"https://doi.org/10.1109/IITC.2000.854082","url":null,"abstract":"The achievable signal-to-noise ratio for an 18-GHz wireless clock distribution system has been estimated by extrapolating from the current status of the clock receiver, the integrated antenna performance, and the understanding of noise sources and coupling mechanisms. It is estimated that a SNR of /spl sim/23 dB is achievable at the input of the frequency divider within the clock receiver block.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123984632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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