A novel via blockage model and its implications

Abstract

Via blockage and its impact on wirability of multi-billion transistor chips are systematically analyzed. Along with a new via distribution based on a stochastic interconnect length distribution and on optimal multilevel interconnect network architecture, a physical via blockage model exploiting channel availability is proposed and applied to analyze future multi-level interconnect networks. This model reveals that the most severe via blockage occurs on first metal level, wasting more than 10% and up to about 50% of wiring area. A new perspective on chip size limit imposed by via blockage is also projected for future chips by using the proposed model.