{"title":"The effects of substrate resistivity on RF component and circuit performance","authors":"B. Floyd, C. Hung, K. O","doi":"10.1109/IITC.2000.854313","DOIUrl":"https://doi.org/10.1109/IITC.2000.854313","url":null,"abstract":"The benefits of using high-resistivity substrates for RF CMOS applications are experimentally quantified. The quality factors of spiral inductors with a patterned ground shield, varactors, and transistors have been measured on both p/sup +/ (with epi) and p/sup -/ substrates, and in each case, Q is higher on p/sup $/substrates. A 5.35-GHz VCO on a p-substrate has an 8 dB lower phase noise than that on a p/sup +/ substrate, while a 7-GHz LNA on a p/sup -/ substrate has a 6 dB higher gain and /spl sim/2.5 dB lower noise figure than that on a p/sup +/ substrate.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132216798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS)","authors":"S. Kobayashi, M. Edahiro, Y. Hayashi","doi":"10.1109/IITC.2000.854266","DOIUrl":"https://doi.org/10.1109/IITC.2000.854266","url":null,"abstract":"We present here the use of the performance predicting ECAD system, which is called Layout-design-based Interconnect Structure Optimization System (LADINOS), for the optimization of multilayer interconnect structures. This system is intended to be used to redesign current ULSI data on possible interconnect structures in the future and to measure the performance of such redesigned ULSIs. Despite the fact that system procedures include chip-size prediction, timing-driven assignment of interconnects to layers, and RC extraction which takes coupling capacitance into account, these procedures are performed very fast. We also give an example of the optimization of multi-layer interconnect structures for use in 0.13 /spl mu/m-generation ULSIs with Al-interconnects.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128555453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Yota, M. Janani, L. Camilletti, A. Kar-Roy, Q.Z. Liu, C. Nguyen, M. D. Woo, J. Hander, P. van Cleemput, W. Chang, W. Chiou, L.J. Li, L. Chao, S. Jang, C. Yu, M. Liang
{"title":"Comparison between HDP CVD and PECVD silicon nitride for advanced interconnect applications","authors":"J. Yota, M. Janani, L. Camilletti, A. Kar-Roy, Q.Z. Liu, C. Nguyen, M. D. Woo, J. Hander, P. van Cleemput, W. Chang, W. Chiou, L.J. Li, L. Chao, S. Jang, C. Yu, M. Liang","doi":"10.1109/IITC.2000.854287","DOIUrl":"https://doi.org/10.1109/IITC.2000.854287","url":null,"abstract":"High-density plasma CVD (HDP CVD) silicon nitride has been investigated for its use in advanced interconnect applications. Results show that the HDP film has many excellent film properties and has many advantages over the plasma-enhanced CVD (PECVD) silicon nitride film. The HDP film has a higher film density, much lower hydrogen content, in addition to lower polish, wet-etch, and dry-etch rates, than the PECVD film. Therefore, the HDP silicon nitride is suitable and ideal as CMP and etch stop layers, as hard mask, and as Copper diffusion and oxidation barriers in damascene architectures.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121564820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Monte-Carlo simulation of electromigration failure distributions of submicron contacts and vias: a new extrapolation methodology for reliability estimate","authors":"J. Huang, A. Oates","doi":"10.1109/IITC.2000.854327","DOIUrl":"https://doi.org/10.1109/IITC.2000.854327","url":null,"abstract":"We have studied the electromigration failure distributions as a function of current density, and we show experimentally that the forms deviate from lognormal distributions as j approaches critical current density. The form change in failure distributions can be well described by Monte-Carlo simulation based on our physical electromigration failure model. The model predicts that median time to fail (MTF) and failure time dispersion (/spl sigma/) approach infinity as j/spl rarr/j/sub c/, and we show that this behavior results from a change in the functional form of failure with current density as j/spl rarr/j/sub c/. We propose a new methodology for the extrapolation of contact and via electromigration data to account for the change in the form of the failure distribution.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"35 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115707961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Kondo, N. Sakuma, Y. Homma, Y. Goto, N. Ohashi, H. Yamaguchi, N. Owada
{"title":"Complete-abrasive-free process for copper damascene interconnection","authors":"S. Kondo, N. Sakuma, Y. Homma, Y. Goto, N. Ohashi, H. Yamaguchi, N. Owada","doi":"10.1109/IITC.2000.854340","DOIUrl":"https://doi.org/10.1109/IITC.2000.854340","url":null,"abstract":"Complete-abrasive-free process for copper (Cu) damascene interconnection has been developed. The process is a combination of a newly developed abrasive-free chemical polishing (AFP) of Cu and dry etching of a barrier metal layer. Complete stop-on-barrier characteristics of Cu polishing are attained by using the new polishing agent and a polyurethane polishing pad. This combination produces a very clean, scratch-free, anticorrosive polished surface, and the total depth of erosion and dishing is reduced to less than one fifth of that produced by conventional slurries even after 100% over polishing. And it is shown that the developed AFP significantly reduces both Cu line resistance and its deviation.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125964893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ruichen Liu, Cheng-Yih Lin, E. Harris, S. Merchant, S. Downey, G. Weber, N. A. Ciampa, W. Tai, W. Lai, M. Morris, J. Bower, J. Miner, J. Frackoviak, W. Mansfield, D. Barr, R. Keller, Chong-Ping Chang, C. Pai, S. Rogers, R. Gregor
{"title":"Single mask metal-insulator-metal (MIM) capacitor with copper damascene metallization for sub-0.18 /spl mu/m mixed mode signal and system-on-a-chip (SoC) applications","authors":"Ruichen Liu, Cheng-Yih Lin, E. Harris, S. Merchant, S. Downey, G. Weber, N. A. Ciampa, W. Tai, W. Lai, M. Morris, J. Bower, J. Miner, J. Frackoviak, W. Mansfield, D. Barr, R. Keller, Chong-Ping Chang, C. Pai, S. Rogers, R. Gregor","doi":"10.1109/IITC.2000.854297","DOIUrl":"https://doi.org/10.1109/IITC.2000.854297","url":null,"abstract":"A one-mask metal-insulator-metal (MIM) capacitor using damascene Ca as the bottom electrode has been developed. Using a PECVD SiN as both the capacitor dielectric and the diffusion barrier for Cu we have demonstrated for the first time, the achieving of low leakage, high linearity MIM capacitors directly on Cu. The leakage and breakdown characteristics of the MIM capacitor depend strongly on both the surface conditions of the damascened Cu and on the PECVD SiN. We found that multilayered SiN is superior than single layer SiN, and Cu CMP plays an important role. However, the inevitable dishing on large area capacitors during Cu CMP shows little impact on the electrical characteristics.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115548488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A three-dimensional stochastic wire-length distribution for variable separation of strata","authors":"J. Joyner, P. Zarkesh-Ha, J.A. Davis, J. Meindl","doi":"10.1109/IITC.2000.854301","DOIUrl":"https://doi.org/10.1109/IITC.2000.854301","url":null,"abstract":"A complete wire-length distribution for future three-dimensional, homogeneous gigascale integrated (GSI) architectures with variable vertical separation of strata is derived. Because stratal pitch was not found to impact the wire-length distribution significantly, bonded three-dimensional implementations which are technologically feasible can be used to obtain large increases in global clock frequencies. The longest interconnect can be reduced by 30% through the introduction of a single additional stratum. A 93% reduction in the length of the longest interconnect can be obtained through the optimal use of a three-dimensional architecture for a 100 nm ASIC, potentially leading to a 15.8 times increase in global clock frequency.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116724421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Demolliens, Y. Morand, M. Fayolle, M. Cochet, M. Assous, H. Feldis, D. Lonis, J. Royer, Y. Gobil, G. Passemard, P. Maury, F. Jourdan, M. Cordeau, T. Morel, L. Perroud, L. Ulmer, J.F. Lugard, D. Renaud
{"title":"Copper-SiOC-AirGap integration in a double level metal interconnect","authors":"O. Demolliens, Y. Morand, M. Fayolle, M. Cochet, M. Assous, H. Feldis, D. Lonis, J. Royer, Y. Gobil, G. Passemard, P. Maury, F. Jourdan, M. Cordeau, T. Morel, L. Perroud, L. Ulmer, J.F. Lugard, D. Renaud","doi":"10.1109/IITC.2000.854347","DOIUrl":"https://doi.org/10.1109/IITC.2000.854347","url":null,"abstract":"This paper describes the integration of Copper with a SiOC/AirGap in a 0.18 /spl mu/m Double Level Metal Interconnect. A new concept is presented to achieve this ultimate interconnect scheme, and its feasibility is demonstrated by a 55% reduction of the total capacitance measured versus a Cu/SiO2 interconnect.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130571453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"When should on-chip inductance modeling become necessary for VLSI timing analysis?","authors":"Li-Fu Chang, Keh-Jeng Chang, R. Mathews","doi":"10.1109/IITC.2000.854315","DOIUrl":"https://doi.org/10.1109/IITC.2000.854315","url":null,"abstract":"Copper-based 0.13 /spl mu/m technologies targeting System-on-a-Chip (SoC) are becoming available for VLSI designs, while aluminum-based 0.18 /spl mu/m and 0.25 /spl mu/m technologies are being used by main-stream, high-end VLSI design groups. Besides material change and technology scaling, other factors that make on-chip inductance modeling become more important are: integration level, harmonic frequency, design style, et al. In essence, many process and layout parameters of today's VLSI designs can have potentially first-order effects on how much inductance modeling affects the timing of a critical net. In this paper, our research result indicate the most critical parameters are material property, process feature size, interconnect length, and driver size. We use typical but critical signal nets in VLSI chips, model them by 3-D RLC extractor, and simulate them by SPICE. This methodology can help identify a proper subset of nets that require detailed RLC-based timing analysis. In this way, more efficient timing analysis without considering inductance modeling (e.g. for SoC) can be performed for other nets.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124025472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Junglong Song, C. Ryu, Heongsoo Kim, Sibum Kim, Chung-Tae Kim, J. Hwang
{"title":"Study on adhesion properties of low dielectric constant films by stud pull test and modified edge lift-off test","authors":"Junglong Song, C. Ryu, Heongsoo Kim, Sibum Kim, Chung-Tae Kim, J. Hwang","doi":"10.1109/IITC.2000.854280","DOIUrl":"https://doi.org/10.1109/IITC.2000.854280","url":null,"abstract":"Adhesion of low-k films to hardmask or underlayer were studied using stud pull test and modified edge lift off test (m-ELT). The adhesion of SiLK to hardmask was enhanced by depositing thin silicon rich oxide layer under conventional PECVD oxide hard mask. The enhancement of adhesion by the Si-rich oxide layer could be attributed to the increase of dangling bonds on the hardmask surface. Adhesion of SiLK to oxide underlayer was degraded by post-anneal at 430/spl deg/C and the above and 5-cycle annealing at 400/spl deg/C. The good correlation between stud pull test and m-ELT was shown in both SiLK and low-k CVD films.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124369039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}