衬底电阻率对射频元件和电路性能的影响

Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-07 DOI:10.1109/IITC.2000.854313

B. Floyd, C. Hung, K. O

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引用次数: 19

摘要

在射频CMOS应用中使用高电阻率衬底的好处是实验量化的。在p/sup +/(用epi)和p/sup -/基片上测量了带图图化接地屏蔽的螺旋电感、变容管和晶体管的质量因子，在每种情况下，p/sup $/基片上的Q更高。p基板上的5.35 ghz压控振荡器的相位噪声比p/sup +/基板上的低8 dB，而p/sup -/基板上的7 ghz LNA的增益比p/sup +/基板上的高6 dB， /spl sim/噪声系数比p/sup +/基板上的低2.5 dB。

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The effects of substrate resistivity on RF component and circuit performance

The benefits of using high-resistivity substrates for RF CMOS applications are experimentally quantified. The quality factors of spiral inductors with a patterned ground shield, varactors, and transistors have been measured on both p/sup +/ (with epi) and p/sup -/ substrates, and in each case, Q is higher on p/sup $/substrates. A 5.35-GHz VCO on a p-substrate has an 8 dB lower phase noise than that on a p/sup +/ substrate, while a 7-GHz LNA on a p/sup -/ substrate has a 6 dB higher gain and /spl sim/2.5 dB lower noise figure than that on a p/sup +/ substrate.

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Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)

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