V. Kolagunta, B. Smith, R. Islam, M. Angyal, J. Mendonca, S. Bartaszewicz, N. Duraiswami, P. Jana, S. Veeraraghavan, S. Venkatesan
{"title":"Inline monitoring of multi-level dual inlaid copper interconnect technologies","authors":"V. Kolagunta, B. Smith, R. Islam, M. Angyal, J. Mendonca, S. Bartaszewicz, N. Duraiswami, P. Jana, S. Veeraraghavan, S. Venkatesan","doi":"10.1109/IITC.2000.854338","DOIUrl":"https://doi.org/10.1109/IITC.2000.854338","url":null,"abstract":"A six level manufacturable copper interconnect technology using metal-first dual inlaid integration for a 0.2 /spl mu/m node is discussed. Various aspects of the technology can be monitored using specially designed resistance measurement structures. Relationship between: (i) inline electrical measurements, (ii) inline physical measurements and (iii) final product characteristics are analyzed and used to window the process flow. This interconnect system can be used to produce microprocessors, SRAMs, and digital signal processors.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126553575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Furusawa, N. Sakuma, D. Ryuzaki, S. Kondo, K. Takeda, Syuntaro Machida, K. Hinode
{"title":"Simple, reliable Cu/low-k interconnect integration using mechanically-strong low-k dielectric material: silicon-oxycarbide","authors":"T. Furusawa, N. Sakuma, D. Ryuzaki, S. Kondo, K. Takeda, Syuntaro Machida, K. Hinode","doi":"10.1109/IITC.2000.854331","DOIUrl":"https://doi.org/10.1109/IITC.2000.854331","url":null,"abstract":"A new low-k material (silicon-oxycarbide, k=3.3) is developed to improve the mechanical strength of Cu/low-k interconnects. The film is shown to be over three-times stronger than conventional ones. The film qualities are high enough: the heat resistance is goad up to 650/spl deg/C, and the breakdown voltage is 55 MV/cm. The film is applied to interconnection test devices without using an oxide-cap. The k remains as low as 3.3, showing that an equivalent capacitance reduction with conventional materials (k=2.5-2.9) can be achieved using a simpler and more reliable structure.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128193875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. F. Chang, V. Roychowdhury, L. Y. Zhang, S. Zhou, Z.Y. Wang, Y.C. Wu, P. Ma, C.S. Lin, Z.J. Kang
{"title":"Multi-I/O and reconfigurable RF/wireless interconnect based on near field capacitive coupling and multiple access techniques","authors":"M. F. Chang, V. Roychowdhury, L. Y. Zhang, S. Zhou, Z.Y. Wang, Y.C. Wu, P. Ma, C.S. Lin, Z.J. Kang","doi":"10.1109/IITC.2000.854269","DOIUrl":"https://doi.org/10.1109/IITC.2000.854269","url":null,"abstract":"Future ULSI interconnect system demands extremely high data transmission rate, multi-I/O service, reconfigurable and fault-tolerant computing/processing architecture and full compatibility with mainstream silicon CMOS and MCM technologies. In this paper, we present a novel RF/wireless interconnect system that provides a unique solution to those system needs. Unlike the traditional \"passive\" metal interconnect, the \"active\" RF/wireless interconnect is based on near-field capacitive coupling, low loss and dispersion-free microwave signal transmission and modern multiple-access algorithms. The proposed RF/wireless interconnect promises ultra-broad bandwidth (up to 100 GHz), simultaneous multi-I/O communications (up to 50/50 I/O sub-channels per shared microwave transmission medium) and reconfigurable network (programmable based on Frequency and/or Code Division Multiple Access). As the first step to prove the feasibility, we have realized a 2/spl times/2 CDMA transceivers based on 0.35 /spl mu/m MOSIS CMOS process, which demonstrates the desired functions of capacitive coupling, guided wave transmission and reconfigurable multiple access.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131792470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Pan, F. Devisch, C. De Tandt, R. Vounckx, M. Kuijk
{"title":"Half-conductive coupling interconnection technology for digital transmission between CMOS chips","authors":"W. Pan, F. Devisch, C. De Tandt, R. Vounckx, M. Kuijk","doi":"10.1109/IITC.2000.854333","DOIUrl":"https://doi.org/10.1109/IITC.2000.854333","url":null,"abstract":"This paper describes for the first time how to use half-conductive coupling (HC-coupling) to obtain digital interconnections between two flip-chipped standard CMOS chips. For process simplicity, the HC-layer can be unpatterned and the CMOS chips do not require any post-processing steps. Due to shielding effects, the technology promises ultra-high-density interconnections.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129376254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Correlation of stress and texture evolution during self- and thermal annealing of electroplated Cu films","authors":"Haebum Lee, S. Lopatin, S. Wong","doi":"10.1109/IITC.2000.854298","DOIUrl":"https://doi.org/10.1109/IITC.2000.854298","url":null,"abstract":"Electroplated Cu films with different plating conditions and different thickness are characterized during self- and thermal annealing. Faster recrystallization and stress development at room temperature are observed as the plating current density and film thickness are increased. Strong correlation between stress and texture behavior is found for all Cu films and is explained by the minimization of surface/interface energy and strain energy in anisotropic metal films.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132917864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Ikeda, T. Hasegawa, K. Tokunaga, M. Fukasawa, H. Kito, T. Miyamoto, S. Kadomura
{"title":"Tungsten via poisoning caused by water trapped in embedded organic low-K dielectrics","authors":"K. Ikeda, T. Hasegawa, K. Tokunaga, M. Fukasawa, H. Kito, T. Miyamoto, S. Kadomura","doi":"10.1109/IITC.2000.854311","DOIUrl":"https://doi.org/10.1109/IITC.2000.854311","url":null,"abstract":"The control of hygroscopicity in dielectric films is one of the key technologies applied in the fabrication of multilevel interconnections. By experiment we identified a new water trap site formation in a silicon dioxide hard mask deposited on organic low-K film. The trapped water causes via poisoning of the organic low-K application in aluminum interconnections with tungsten electrodes. We showed that by inserting an out-gassing step and using a chemically formed film we can avoid this problem.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114432097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Kobayashi, A. Sano, H. Akahoshi, T. Itabashi, T. Haba, S. Fukada, H. Miyazaki
{"title":"Trench and via filling profile simulations for copper electroplating process","authors":"K. Kobayashi, A. Sano, H. Akahoshi, T. Itabashi, T. Haba, S. Fukada, H. Miyazaki","doi":"10.1109/IITC.2000.854273","DOIUrl":"https://doi.org/10.1109/IITC.2000.854273","url":null,"abstract":"We have developed a simulation method to calculate filling profile in sub-micron scale trenches and vias using Cu electroplating. The physical properties (diffusivity and surface reaction rate) of additives are directly incorporated in the boundary condition of this method so that the effects of physical properties of the additives on profile of filling can be evaluated. Using this method, we clarified that micro-knobs and overhangs on seed layer are important for creating a void or seam in the Cu film.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114478215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Characterization and integration of porous extra low-k (XLK) dielectrics","authors":"C. Jin, J. Wetzel","doi":"10.1109/IITC.2000.854294","DOIUrl":"https://doi.org/10.1109/IITC.2000.854294","url":null,"abstract":"Porous XLK dielectric films have been characterized and integrated into one level metal Cu damascene test structures. The material shows reduced dielectric constant as well as lower modulus compared with dense HSQ. Initial one level metal Cu/XLK damascene integration studies demonstrate the feasibility and issues associated with the use of porous low-k materials. Parametric test data show good capacitance and leakage current distributions.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114527082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Verove, B. Descouts, P. Gayet, M. Guillermet, E. Sabouret, E. Spinelli, E. van der Vegt
{"title":"Dual damascene architectures evaluation for the 0.18 /spl mu/m technology and below","authors":"C. Verove, B. Descouts, P. Gayet, M. Guillermet, E. Sabouret, E. Spinelli, E. van der Vegt","doi":"10.1109/IITC.2000.854344","DOIUrl":"https://doi.org/10.1109/IITC.2000.854344","url":null,"abstract":"This paper compares three different schemes to pattern dual damascene (DD) structures. The Self Aligned (SA), Via First (VF), and Trench First (TF) architectures are compared in terms of complexity, process latitude, and sensitivity to lithography misalignment using 0.18-/spl mu/m copper/oxide two metal level structures. The integration of thick metal lines is also discussed, for the upper levels of interconnects. This study shows that the VF architecture has the best via chain yield, regardless of the test configuration, and allows to pattern thick metal DD structures with high yield. The VF technique was used to manufacture a six copper level device, with functional yield similar to that obtained with an AlCu/HSQ Back End Of Line (BEOL).","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128702574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Hattori, H. Masuda, H. Sato, T. Matsuda, A. Yamamoto, Y. Kato, S. Ogawa, A. Ohsaki, T. Ueda
{"title":"0.42 /spl mu/m contacted pitch dual damascene copper interconnect for 0.15 /spl mu/m EDRAM using tapered via aligned to trench","authors":"T. Hattori, H. Masuda, H. Sato, T. Matsuda, A. Yamamoto, Y. Kato, S. Ogawa, A. Ohsaki, T. Ueda","doi":"10.1109/IITC.2000.854310","DOIUrl":"https://doi.org/10.1109/IITC.2000.854310","url":null,"abstract":"A tapered via aligned to a trench without any expanding of trench width for 0.42 /spl mu/m contacted pitch dual damascene Cu interconnect has been studied. Cu via filling and via electrical properties were dependent on shapes of vias, and it has been found that the aligned tapered via has advantages for the fine pitch Cu dual damascene interconnect.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125449957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}