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Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)最新文献

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Picosecond ultrasonic study of the electrical and mechanical properties of CoSi/sub 2/ formed under Ti and TiN cap layers 皮秒超声研究Ti和TiN帽层下CoSi/sub - 2/的电学和力学性能
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854318
R. Stoner, G. Tas, C. Morath, H. Maris, Lee Chen, H. Chuang, Chi-Tung Huang, Y. Hwang
{"title":"Picosecond ultrasonic study of the electrical and mechanical properties of CoSi/sub 2/ formed under Ti and TiN cap layers","authors":"R. Stoner, G. Tas, C. Morath, H. Maris, Lee Chen, H. Chuang, Chi-Tung Huang, Y. Hwang","doi":"10.1109/IITC.2000.854318","DOIUrl":"https://doi.org/10.1109/IITC.2000.854318","url":null,"abstract":"We report noncontact measurements of CoSi/sub 2/ layers made using a commercial picosecond ultrasonic system. The layers were formed in a two step RTP-process beginning with samples with nominally 120 /spl Aring/ Co capped with either 150 /spl Aring/ PVD TiN, or 100 /spl Aring/ PVD Ti. The thickness, roughness and electrical resistivity of the final disilicide layers were investigated as functions of the first anneal temperature. The results indicate that the TiN-capped process yields a significantly smoother and more conductive disilicide film than the Ti-capped process over a wide range of first anneal temperatures.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126693118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Reaction barrier formation of W/poly-Si gate by NH/sub 3/ rapid thermal annealing applicable to 0.15 /spl mu/m CMOS devices 适用于0.15 /spl mu/m CMOS器件的NH/sub /快速热退火W/多晶硅栅极反应势垒形成
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854284
Chang-Hee Han, D. Sohn, Ji-Soo Park, J. Bae, J. Lee, Min-Soo Park, J. Oh, J. Park
{"title":"Reaction barrier formation of W/poly-Si gate by NH/sub 3/ rapid thermal annealing applicable to 0.15 /spl mu/m CMOS devices","authors":"Chang-Hee Han, D. Sohn, Ji-Soo Park, J. Bae, J. Lee, Min-Soo Park, J. Oh, J. Park","doi":"10.1109/IITC.2000.854284","DOIUrl":"https://doi.org/10.1109/IITC.2000.854284","url":null,"abstract":"We found that an NH/sub 3/ rapid thermal annealing of Wi/poly-Si gate above 750/spl deg/C resulted in the formation of a highly reliable in-situ barrier layer and low resistivity W, simultaneously. This barrier layer kept the Wi/poly-Si gate stable up to the elevated temperature of 1000/spl deg/C. Ammonia treated W/poly-Si gate showed a narrow distribution of sheet resistance at a line width of 0.15 /spl mu/m after the post annealing at 900/spl deg/C for 30 min. This W/poly-Si gate was acceptable to apply to 0.15 /spl mu/m CMOS devices without deposition of a barrier layer.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126234908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of the roles of the additive components for second generation copper electroplating chemistries used for advanced interconnect metalization 用于先进互连金属化的第二代镀铜化学添加剂的作用研究
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854299
R. Mikkola, Lin-lin Chen
{"title":"Investigation of the roles of the additive components for second generation copper electroplating chemistries used for advanced interconnect metalization","authors":"R. Mikkola, Lin-lin Chen","doi":"10.1109/IITC.2000.854299","DOIUrl":"https://doi.org/10.1109/IITC.2000.854299","url":null,"abstract":"This paper discusses the effects of the emerging second generation copper electrochemical deposition (ECD) bath additives on the fill mechanism for advanced interconnect trenches. The role of the accelerator (organic disulfides) and suppressor (polymers) for a two component additive package was evaluated. In addition the effects of the polymer-Cl interaction on the fill mechanism as a function of chloride ion concentration was explored. SEM cross sections of partially filled electroplated copper trenches show a two stage fill mechanism consisting of (1) conformal fill followed by (2) bottom-up fill. It was determined that the polymer-Cl complex plays a critical role during the initial stages of fill for sub one-micron trenches.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114191004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Integration of low-k spin-on polymer and Cu for Damascene 低钾自旋聚合物与Cu在Damascene中的集成
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854288
W. Chang, W. Chiou, L.J. Li, L. Chao, S. Jang, C. Yu, M. Liang
{"title":"Integration of low-k spin-on polymer and Cu for Damascene","authors":"W. Chang, W. Chiou, L.J. Li, L. Chao, S. Jang, C. Yu, M. Liang","doi":"10.1109/IITC.2000.854288","DOIUrl":"https://doi.org/10.1109/IITC.2000.854288","url":null,"abstract":"Integration of low-k spin-on polymer (SOP, k 2.7) and Cu for damascene by patterning via first and trench secondly has been investigated. Interconnect failure caused by DUV photoresist residues in via hole after trench photo development has been identified. The photoresist residue can be eliminated by proper surface treatment after via etching and a tight Rc-via distribution is demonstrated. In addition, the compatibility of SOP and chemical mechanical polish (CMP) was also studied. Good Rs and leakage distributions are obtained by optimizing Cu/TaN and oxide polish. Pressure cook test, temperature cycling and thermal anneal has been performed to test the reliability of UV-treated SOP/Cu damascene and no degradation in Cu resistance, line-to-line capacitance (C,,), and leakage has been found.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127759858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Cu dual damascene process for 0.13 um technology generation using self ion sputtering (SIS) with ion reflector 利用带离子反射器的自离子溅射(SIS)技术生成0.13 um铜双大马士革工艺
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854296
J. Wada, A. Sakata, H. Matsuyama, K. Watanabe, T. Katata
{"title":"Cu dual damascene process for 0.13 um technology generation using self ion sputtering (SIS) with ion reflector","authors":"J. Wada, A. Sakata, H. Matsuyama, K. Watanabe, T. Katata","doi":"10.1109/IITC.2000.854296","DOIUrl":"https://doi.org/10.1109/IITC.2000.854296","url":null,"abstract":"Newly developed self ion sputtering(SIS) system is applied to Cu seed formation for electroplating (EP)-Cu filling. SIS is a bias sputtering using Cu/sup +/ ions generated by self sustained Cu plasma with controlling ion flux to a substrate by an ion reflector. This method can be realized by small modification of long throw sputtering (LTS) configuration. Substrate bias promotes transportation of Cu ions to the bottom of via holes efficiently from Cu plasma, which leads to improve step coverage. However, in the case of only applying substrate bias, uniformity of step coverage across the wafer can not be achieved to the objective value. Ion reflector converges ions on the wafer, especially on the edge of the wafer, then it improves uniformity of step coverage across the wafer. EP-Cu filling of vias of 0.2 um, A/R of 4 can be obtained using this method. Moreover, vias of 0.17 um, A/R of 5 can be completely filled when SIS is applied to barrier metal (TaN) deposition due to drastic improvement of TaN coverage.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"45 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133589498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-frequency noise measurement of copper damascene interconnects 铜大马士革互连的低频噪声测量
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854309
L. Koh, L. W. Chu, K. Pey, W. Chim
{"title":"Low-frequency noise measurement of copper damascene interconnects","authors":"L. Koh, L. W. Chu, K. Pey, W. Chim","doi":"10.1109/IITC.2000.854309","DOIUrl":"https://doi.org/10.1109/IITC.2000.854309","url":null,"abstract":"This paper presents results of using low-frequency noise measurement to characterize the quality and reliability of state-of-the-art copper damascene interconnects. Wafer-level low-frequency noise measurement was performed under high current density on a conventional NIST test structure with various copper line-widths. The Cu test structures were capped with a bilayer of silicon nitride and silicon oxide to prevent formation of copper oxide on its surface. Low-frequency noise measurement was found to be a more sensitive monitor than solely resistance measurement for assessing the quality and reliability of long copper signal lines. The magnitude of the flicker (or 1/f) noise was found to be related to the physical void formation along the line.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123066136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Microstructure evolution of electroplated Cu during room temperature transient 室温瞬态电镀Cu的微观组织演变
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854321
M. Gribelyuk, S. Malhotra, P. Locke, P. Dehaven, J. Fluegel, C. Parks, A. Simon, R. Murphy
{"title":"Microstructure evolution of electroplated Cu during room temperature transient","authors":"M. Gribelyuk, S. Malhotra, P. Locke, P. Dehaven, J. Fluegel, C. Parks, A. Simon, R. Murphy","doi":"10.1109/IITC.2000.854321","DOIUrl":"https://doi.org/10.1109/IITC.2000.854321","url":null,"abstract":"Previously the Cu resistance transient time was found to be dependent on the electroplating current. It was shown that longer transient times were correlated with a greater incorporation of plating impurities for the bath chemistry used in this study. The present work shows that the grain growth that occurs during the resistance transient is initiated by the formation of abnormally large grains, where the transformed structure reveals strong /spl Sigma/3 type twinning. The increase in the fraction of twin grain boundaries with transient time is quantified, and a comparison of the time dependencies of resistivity and the grain size shows that the Mayadas-Shatzkes model can qualitatively describe grain boundary resistivity. X-ray analysis revealed that the structure is strongly {111} textured and the contribution of {200} texture increases during transformation. Atomic Force Microscopy (AFM) and imaging with the secondary electron in-lens detector showed that surface morphology of Cu structures varies across the film and is dependent on the plating current.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122322168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Integration of copper and fluorosilicate glass for 0.18 /spl mu/m interconnections 铜和氟硅酸盐玻璃的集成，用于0.18 /spl mu/m互连
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854330
E. Barth, T. Ivers, P. McLaughlin, A. McDonald, E. Levine, S. Greco, J. Fitzsimmons, I. Melville, T. Spooner, C. Dewan, X. Chen, D. Manger, H. Nye, V. McGahay, G. Biery, R. Goldblatt, T. Chen
{"title":"Integration of copper and fluorosilicate glass for 0.18 /spl mu/m interconnections","authors":"E. Barth, T. Ivers, P. McLaughlin, A. McDonald, E. Levine, S. Greco, J. Fitzsimmons, I. Melville, T. Spooner, C. Dewan, X. Chen, D. Manger, H. Nye, V. McGahay, G. Biery, R. Goldblatt, T. Chen","doi":"10.1109/IITC.2000.854330","DOIUrl":"https://doi.org/10.1109/IITC.2000.854330","url":null,"abstract":"The integration of dual damascene copper with fluorosilicate glass (FSC) at the 0.18 /spl mu/m technology node is described. The BEOL structure has been implemented for an advanced CMOS technology, and along with an SOI FEOL is being used for high performance logic and SRAM devices. Reliability and yield is shown to be equivalent to a similar technology without FSG. Key considerations in the development of this technology are presented.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127704726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Copper dual damascene integration using organic low k material: construction architecture comparison 铜双大马士革一体化采用有机低k材料:建筑结构比较
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854332
Y. Morand, M. Assous, P. Berruyer, M. Cochet, O. Demolliens, M. Fayolle, D. Louis, G. Passemard, A. Roman, C. Verove, Y. Trouiller
{"title":"Copper dual damascene integration using organic low k material: construction architecture comparison","authors":"Y. Morand, M. Assous, P. Berruyer, M. Cochet, O. Demolliens, M. Fayolle, D. Louis, G. Passemard, A. Roman, C. Verove, Y. Trouiller","doi":"10.1109/IITC.2000.854332","DOIUrl":"https://doi.org/10.1109/IITC.2000.854332","url":null,"abstract":"This paper presents three integration schemes of copper with a pure organic low k material (SiLK/sup TM/, Dow Chemical Co., k=2.8). We will compare two trench first architectures, leading to a self or not self aligned structure, with the more conventional self aligned \"Via First at Via Level\" structure. The limitations of the self aligned structures are discussed by comparison with results obtained with SiO2.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134405283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A super low-k (k=1.1) silica aerogel film using supercritical drying technique 采用超临界干燥技术制备超低k (k=1.1)二氧化硅气凝胶膜
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854306
N. Kawakami, Y. Fukumoto, T. Kinoshita, K. Suzuki, Keita Inoue
{"title":"A super low-k (k=1.1) silica aerogel film using supercritical drying technique","authors":"N. Kawakami, Y. Fukumoto, T. Kinoshita, K. Suzuki, Keita Inoue","doi":"10.1109/IITC.2000.854306","DOIUrl":"https://doi.org/10.1109/IITC.2000.854306","url":null,"abstract":"A porous silica aerogel film as low-k dielectric is demonstrated for the first time. An \"on-wafer\" gelation technique in ammonium hydroxide vapor is developed to enhance the process compatibility with the conventional spin-on dielectric process in ULSI technology. By using a supercritical drying process, which is free from capillary forces, a high porosity aerogel film with a k value of 1.1 is obtained.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"464 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113986522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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