{"title":"变地层分离的三维随机线长分布","authors":"J. Joyner, P. Zarkesh-Ha, J.A. Davis, J. Meindl","doi":"10.1109/IITC.2000.854301","DOIUrl":null,"url":null,"abstract":"A complete wire-length distribution for future three-dimensional, homogeneous gigascale integrated (GSI) architectures with variable vertical separation of strata is derived. Because stratal pitch was not found to impact the wire-length distribution significantly, bonded three-dimensional implementations which are technologically feasible can be used to obtain large increases in global clock frequencies. The longest interconnect can be reduced by 30% through the introduction of a single additional stratum. A 93% reduction in the length of the longest interconnect can be obtained through the optimal use of a three-dimensional architecture for a 100 nm ASIC, potentially leading to a 15.8 times increase in global clock frequency.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"53","resultStr":"{\"title\":\"A three-dimensional stochastic wire-length distribution for variable separation of strata\",\"authors\":\"J. Joyner, P. Zarkesh-Ha, J.A. Davis, J. Meindl\",\"doi\":\"10.1109/IITC.2000.854301\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A complete wire-length distribution for future three-dimensional, homogeneous gigascale integrated (GSI) architectures with variable vertical separation of strata is derived. Because stratal pitch was not found to impact the wire-length distribution significantly, bonded three-dimensional implementations which are technologically feasible can be used to obtain large increases in global clock frequencies. The longest interconnect can be reduced by 30% through the introduction of a single additional stratum. A 93% reduction in the length of the longest interconnect can be obtained through the optimal use of a three-dimensional architecture for a 100 nm ASIC, potentially leading to a 15.8 times increase in global clock frequency.\",\"PeriodicalId\":287825,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"53\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2000.854301\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2000.854301","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A three-dimensional stochastic wire-length distribution for variable separation of strata
A complete wire-length distribution for future three-dimensional, homogeneous gigascale integrated (GSI) architectures with variable vertical separation of strata is derived. Because stratal pitch was not found to impact the wire-length distribution significantly, bonded three-dimensional implementations which are technologically feasible can be used to obtain large increases in global clock frequencies. The longest interconnect can be reduced by 30% through the introduction of a single additional stratum. A 93% reduction in the length of the longest interconnect can be obtained through the optimal use of a three-dimensional architecture for a 100 nm ASIC, potentially leading to a 15.8 times increase in global clock frequency.