铜双大马士革互连与非常低k介电目标为130纳米节点

Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI:10.1109/IITC.2000.854345

H. Kudo, Y. Yoshie, S. Yamaguchi, K. Watanabe, M. Ikeda, K. Kakamu, T. Hosoda, K. Ohhira, N. Santoh, N. Misawa, K. Matsuno, Y. Wakasugi, A. Hasegawa, K. Nagase, T. Suzuki

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引用次数: 6

摘要

由于极低k (VLK)材料导热性差，所谓的全低k层间介电(ILD)结构可能会降低Cu布线的可靠性，这是一个非常值得关注的问题。我们在这项工作中提出的ILD结构(称为混合型)由VLK(沟槽电平)和SiO/sub 2/(通孔电平)组成，以满足以下两个要求;减小布线电容，而不降低导热系数。在这项工作中，我们提出了双大马士革图案化和Cu金属化的杂化结构的集成。

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Copper dual damascene interconnects with very low-k dielectrics targeting for 130 nm node

It is a great concern that a so-called full low-k interlayer dielectric (ILD) structure may degrade reliability of Cu wiring due to the poor thermal conductivity of very low-k (VLK) material. An ILD structure we proposed in this work (named hybrid) are made of VLK for the trench level and SiO/sub 2/ for the via level, to meet following two requirements; reducing wiring capacitance and not decreasing thermal conductivity so much. In this work, we have presented integration of dual damascene patterning and Cu metallization for the hybrid structure.

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Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)

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