{"title":"片上无线时钟信号分配的信噪比估计(2000年)","authors":"D. Bravo, H. Yoon, Kihong Kim, B. Floyd, K. O","doi":"10.1109/IITC.2000.854082","DOIUrl":null,"url":null,"abstract":"The achievable signal-to-noise ratio for an 18-GHz wireless clock distribution system has been estimated by extrapolating from the current status of the clock receiver, the integrated antenna performance, and the understanding of noise sources and coupling mechanisms. It is estimated that a SNR of /spl sim/23 dB is achievable at the input of the frequency divider within the clock receiver block.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Estimation of the signal-to-noise ratio for on-chip wireless clock signal distribution (year 2000)\",\"authors\":\"D. Bravo, H. Yoon, Kihong Kim, B. Floyd, K. O\",\"doi\":\"10.1109/IITC.2000.854082\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The achievable signal-to-noise ratio for an 18-GHz wireless clock distribution system has been estimated by extrapolating from the current status of the clock receiver, the integrated antenna performance, and the understanding of noise sources and coupling mechanisms. It is estimated that a SNR of /spl sim/23 dB is achievable at the input of the frequency divider within the clock receiver block.\",\"PeriodicalId\":287825,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2000.854082\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2000.854082","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Estimation of the signal-to-noise ratio for on-chip wireless clock signal distribution (year 2000)
The achievable signal-to-noise ratio for an 18-GHz wireless clock distribution system has been estimated by extrapolating from the current status of the clock receiver, the integrated antenna performance, and the understanding of noise sources and coupling mechanisms. It is estimated that a SNR of /spl sim/23 dB is achievable at the input of the frequency divider within the clock receiver block.