Multilevel test structures for metal CMP integration application to Cu/SiO/sub 2/ damascene interconnect

Abstract

This paper presents a method to evaluate the metal CMP impact on the performance of multilevel interconnect. For this purpose specific two metal level test structures have been defined, after a brief description of these structures, we present the results obtained on a Cu/SiO/sub 2/ dual damascene architecture. It is shown that the upper metal yield is drastically degraded by the underlying metal layer patterns. Therefore a two levels study is essential to integrate a metal CMP in a multilevel metallization.