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Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)最新文献

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The investigation of galvanic corrosion in post-copper-CMP cleaning 铜- cmp清洗后电偶腐蚀的研究
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854341
H.C. Chen, M.S. Yang, J.Y. Wu, V. Wang
{"title":"The investigation of galvanic corrosion in post-copper-CMP cleaning","authors":"H.C. Chen, M.S. Yang, J.Y. Wu, V. Wang","doi":"10.1109/IITC.2000.854341","DOIUrl":"https://doi.org/10.1109/IITC.2000.854341","url":null,"abstract":"The characteristics of galvanic corrosion in post-copper CMP cleaning are investigated. This type of corrosion occurs when CMP process completed, due to the heating lamp in SRD step. Particularly, it occurs only in device wafer, but not in structural test wafer. The corrosion behavior with light was identified. It occurs not only in integrated cleaner, but also in stand alone brush type cleaner. Copper lines were bridged after corrosion. The corrosion by-product can be removed by means of solvent cleaning. The mechanism and the prevention of this type of light-induced corrosion are reported in this paper.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122437801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Quantitative analysis on Cu diffusion through TaN barrier metal and the device degradation by using two-level Cu-interconnects implemented 0.25 /spl mu/m-256 Mbit DRAMs 采用实现0.25 /spl mu/m-256 Mbit dram的两级Cu互连，定量分析Cu在TaN阻挡金属中的扩散和器件退化
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854324
T. Kawanoue, T. Iijima, T. Matsuda, Y. Yamada, M. Morikado, K. Sugimae, T. Kajiyama, H. Maekawa, T. Hamamoto, J. Kumagai, H. Kaneko, N. Hayasaka
{"title":"Quantitative analysis on Cu diffusion through TaN barrier metal and the device degradation by using two-level Cu-interconnects implemented 0.25 /spl mu/m-256 Mbit DRAMs","authors":"T. Kawanoue, T. Iijima, T. Matsuda, Y. Yamada, M. Morikado, K. Sugimae, T. Kajiyama, H. Maekawa, T. Hamamoto, J. Kumagai, H. Kaneko, N. Hayasaka","doi":"10.1109/IITC.2000.854324","DOIUrl":"https://doi.org/10.1109/IITC.2000.854324","url":null,"abstract":"To evaluate Cu diffusion in a practically used damascene structure, plasma-enhanced CVD-SiO/sub 2/ (p-SiO/sub 2/) layer with trench test structure was used, and trace Cu diffusion into the p-SiO/sub 2/ trench through TaN barrier metal was quantified by precise chemical analysis for the first time. In the trench structure, the diffused Cu amount was 2 orders of magnitude larger than that in the blanket structure. This increase in the trench structure has been well explained by the obtained Cu diffusion coefficient in TaN and the TaN step coverage at the trench sidewall. Two-level Cu interconnects have been implemented for the 0.25 /spl mu/m 256 M bit-DRAM, and the retention time decrease after annealing has been examined in related to Cu diffusion. The result suggested the possibility that the Cu in the ILD on the order of 10/sup 16/ atoms/cm/sup 3/ affected the DRAM cell function.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122462012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Integration and reliability of copper magnesium alloys for multilevel interconnects 多级互连用铜镁合金的集成与可靠性
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854335
Gregor Braeckelmann, Ramnath Venkatraman, Cristiano Capasso, Matthew Herrick
{"title":"Integration and reliability of copper magnesium alloys for multilevel interconnects","authors":"Gregor Braeckelmann, Ramnath Venkatraman, Cristiano Capasso, Matthew Herrick","doi":"10.1109/IITC.2000.854335","DOIUrl":"https://doi.org/10.1109/IITC.2000.854335","url":null,"abstract":"This paper discusses the deposition, integration, performance, and reliability of copper-magnesium alloys in interconnect structures for state of the art integrated circuits. A detailed discussion of process-related characteristics will be presented. Special emphasis is given here on the adhesion and diffusion properties of copper-magnesium. Furthermore, electrical performance of test structures using copper-magnesium and results from electromigration testing are being presented.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122513692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Electromigration in multi-level interconnects with polymeric low-k interlevel dielectrics 聚合物低k介电层间多层互连中的电迁移
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854325
P. Justison, E. Ogawa, M. Gall, C. Capasso, D. Jawarani, J. Wetzel, H. Kawasaki, P. Ho
{"title":"Electromigration in multi-level interconnects with polymeric low-k interlevel dielectrics","authors":"P. Justison, E. Ogawa, M. Gall, C. Capasso, D. Jawarani, J. Wetzel, H. Kawasaki, P. Ho","doi":"10.1109/IITC.2000.854325","DOIUrl":"https://doi.org/10.1109/IITC.2000.854325","url":null,"abstract":"Electromigration (EM) characteristics were evaluated on multi-level Al(Cu) test structures with polymeric low k and standard oxide interlevel dielectrics. The two polymers used as interlevel dielectrics in this work are a fluorinated polyimide (FPI) and a poly(aryl) ether(PAE). Joule heating experiments and microstructural analysis were both conducted on Al(Cu) to insure that that there were no microstructural or other differences between the polymer samples and their oxide counterparts. The results show that the integration of polymeric low k dielectrics has a significant impact on EM performance of interconnect structures.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"417 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122795489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
New strategy to improve the mechanical strength and to reduce potential contamination of dielectric materials for double level metal integration 双能级金属集成中提高介质材料机械强度和减少潜在污染的新策略
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854291
M. Assous, Y. Morand, O. Demolliens, P. Berruyer, B. Manierre, Y. Gobil, D. Louis, H. Feldis, C. Vizioz, A. Roman
{"title":"New strategy to improve the mechanical strength and to reduce potential contamination of dielectric materials for double level metal integration","authors":"M. Assous, Y. Morand, O. Demolliens, P. Berruyer, B. Manierre, Y. Gobil, D. Louis, H. Feldis, C. Vizioz, A. Roman","doi":"10.1109/IITC.2000.854291","DOIUrl":"https://doi.org/10.1109/IITC.2000.854291","url":null,"abstract":"This work concerns a new strategy for dual damascene Cu/low k integration in order to improve the mechanical strength and to reduce the contamination of the dielectric materials. We introduce the spacer concept in the dual damascene integration scheme with SiLK(R) dielectric. Two materials have been studied as spacers: SiN and TiN. The comparison is based on morphological aspects as well as electrical CD and Kelvin via resistance measurements for different strategies.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123783507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Clock distribution networks with on-chip transmission lines 带有片上传输线的时钟分配网络
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854080
Masayuki Mizuno, Kenichiro, Yoshikazu Sumi, Muneo Fukaishi, Hitoshi Wakabayashi, Tohru Mogami, Tadahiko Horiuchi, Masakazu Yamashina
{"title":"Clock distribution networks with on-chip transmission lines","authors":"Masayuki Mizuno, Kenichiro, Yoshikazu Sumi, Muneo Fukaishi, Hitoshi Wakabayashi, Tohru Mogami, Tadahiko Horiuchi, Masakazu Yamashina","doi":"10.1109/IITC.2000.854080","DOIUrl":"https://doi.org/10.1109/IITC.2000.854080","url":null,"abstract":"Today's fabrication process scaling enables on-chip lossy transmission lines to be used for long interconnects and high-speed clocking. Advantages and design tradeoffs of on-chip transmission lines are discussed and a 100-mm/sup 2/ 5-GHz clocking chip using on-chip transmission lines is introduced.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128929654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A thick-Cu process for add-on interconnections using photosensitive varnish for thick interlayer dielectric 一种用于附加互连的厚铜工艺，使用光敏清漆作为厚层介电介质
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854300
K. Saito, T. Kosugi, S. Yagi, C. Yamaguchi, K. Kudo, M. Yano, T. Kumazaki, M. Yaita, H. Ishii, K. Machida, H. Kyuragi
{"title":"A thick-Cu process for add-on interconnections using photosensitive varnish for thick interlayer dielectric","authors":"K. Saito, T. Kosugi, S. Yagi, C. Yamaguchi, K. Kudo, M. Yano, T. Kumazaki, M. Yaita, H. Ishii, K. Machida, H. Kyuragi","doi":"10.1109/IITC.2000.854300","DOIUrl":"https://doi.org/10.1109/IITC.2000.854300","url":null,"abstract":"A thick-Cu process suitable for the fabrication of add-on interconnections for microwave passive elements on ULSIs has been developed. The following three novel techniques were employed: electroless plating for a Ru/Ni cap layer on a Cu film to prevent oxidation, a simple thick-Cu interconnection fabrication process using a positive-type photosensitive varnish, and a thick interlayer dielectric film (/spl epsi/=2.9) under the Cu interconnections to reduce RF power loss in a regular silicon substrate. By using these techniques, spiral inductors with high quality factors (Q/sub max/ of 38) and a co-planar waveguide with low losses (<0.2 dB/mm) were obtained.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125309607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Optimal repeater insertion for n-tier multilevel interconnect architectures n层多层互连结构的最佳中继器插入
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854303
R. Venkatesan, J.A. Davis, K. Bowman, J. Meindl
{"title":"Optimal repeater insertion for n-tier multilevel interconnect architectures","authors":"R. Venkatesan, J.A. Davis, K. Bowman, J. Meindl","doi":"10.1109/IITC.2000.854303","DOIUrl":"https://doi.org/10.1109/IITC.2000.854303","url":null,"abstract":"A new methodology to optimally insert repeaters for n-tier multilevel interconnect architectures is demonstrated. For a 0.1 /spl mu/m ASIC macrocell case study, repeater insertion either decreases the macrocell area 4-fold (and lowers power dissipation by 50%), increases clock frequency by 22% or reduces number of metal levels by 25%.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133110072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
IEEE 2000 International Interconnect Technology Conference IEEE 2000国际互连技术会议
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 1900-01-01 DOI: 10.1109/iitc.2000.854077
H. Hotel
{"title":"IEEE 2000 International Interconnect Technology Conference","authors":"H. Hotel","doi":"10.1109/iitc.2000.854077","DOIUrl":"https://doi.org/10.1109/iitc.2000.854077","url":null,"abstract":"","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116908867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Preliminary study on dependency of basic properties of porous silica ILD thin film on CMP compatibility 多孔二氧化硅ILD薄膜基本性能对CMP相容性影响的初步研究
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 1900-01-01 DOI: 10.1109/IITC.2000.854282
H. Hanahata, M. Miyamoto, T. Kamata, S. Matsuno, T. Tanabe
{"title":"Preliminary study on dependency of basic properties of porous silica ILD thin film on CMP compatibility","authors":"H. Hanahata, M. Miyamoto, T. Kamata, S. Matsuno, T. Tanabe","doi":"10.1109/IITC.2000.854282","DOIUrl":"https://doi.org/10.1109/IITC.2000.854282","url":null,"abstract":"Adhesion, cohesive strength, modulus, and hardness of the porous silica ILD film via organic/inorganic hybrid (ALCAP-S) with various kinds of film thickness were investigated and the preliminary attempt was made to correlate the above properties with abrasion compatibility as a function of film thickness. The Stud-pull strength is drastically affected by the visco-elastic behavior of the film and necessary for correction. The corrected adhesion and cohesive strength of ALCAP-S (k=2.2) are satisfactorily high. With decreasing the film thickness, the depth-dependency of modulus induced by the substrate becomes more significant and the corresponding film is liable to abrasion. On the contrary, with increasing thickness the dependency ceases and the film appears to be more elastic, leading to lower abrasion compatibility.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126412045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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