Clock distribution networks with on-chip transmission lines

Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI:10.1109/IITC.2000.854080

Masayuki Mizuno, Kenichiro, Yoshikazu Sumi, Muneo Fukaishi, Hitoshi Wakabayashi, Tohru Mogami, Tadahiko Horiuchi, Masakazu Yamashina

引用次数: 13

Abstract

Today's fabrication process scaling enables on-chip lossy transmission lines to be used for long interconnects and high-speed clocking. Advantages and design tradeoffs of on-chip transmission lines are discussed and a 100-mm/sup 2/ 5-GHz clocking chip using on-chip transmission lines is introduced.

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带有片上传输线的时钟分配网络

今天的制造工艺缩放使片上损耗传输线用于长互连和高速时钟。讨论了片上传输线的优点和设计权衡，并介绍了一种采用片上传输线的100mm /sup 2/ 5ghz时钟芯片。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)

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