Optimal repeater insertion for n-tier multilevel interconnect architectures

Abstract

A new methodology to optimally insert repeaters for n-tier multilevel interconnect architectures is demonstrated. For a 0.1 /spl mu/m ASIC macrocell case study, repeater insertion either decreases the macrocell area 4-fold (and lowers power dissipation by 50%), increases clock frequency by 22% or reduces number of metal levels by 25%.