n层多层互连结构的最佳中继器插入

Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI:10.1109/IITC.2000.854303

R. Venkatesan, J.A. Davis, K. Bowman, J. Meindl

{"title":"n层多层互连结构的最佳中继器插入","authors":"R. Venkatesan, J.A. Davis, K. Bowman, J. Meindl","doi":"10.1109/IITC.2000.854303","DOIUrl":null,"url":null,"abstract":"A new methodology to optimally insert repeaters for n-tier multilevel interconnect architectures is demonstrated. For a 0.1 /spl mu/m ASIC macrocell case study, repeater insertion either decreases the macrocell area 4-fold (and lowers power dissipation by 50%), increases clock frequency by 22% or reduces number of metal levels by 25%.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Optimal repeater insertion for n-tier multilevel interconnect architectures\",\"authors\":\"R. Venkatesan, J.A. Davis, K. Bowman, J. Meindl\",\"doi\":\"10.1109/IITC.2000.854303\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new methodology to optimally insert repeaters for n-tier multilevel interconnect architectures is demonstrated. For a 0.1 /spl mu/m ASIC macrocell case study, repeater insertion either decreases the macrocell area 4-fold (and lowers power dissipation by 50%), increases clock frequency by 22% or reduces number of metal levels by 25%.\",\"PeriodicalId\":287825,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2000.854303\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2000.854303","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

提出了一种优化n层多层互连结构中继器插入的新方法。对于0.1 /spl mu/m的ASIC macrocell案例研究，插入中继器可以将macrocell面积减少4倍(并降低50%的功耗)，将时钟频率增加22%或将金属电平数量减少25%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Optimal repeater insertion for n-tier multilevel interconnect architectures

A new methodology to optimally insert repeaters for n-tier multilevel interconnect architectures is demonstrated. For a 0.1 /spl mu/m ASIC macrocell case study, repeater insertion either decreases the macrocell area 4-fold (and lowers power dissipation by 50%), increases clock frequency by 22% or reduces number of metal levels by 25%.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)

自引率

0.00%

发文量