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Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)最新文献

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Effect of W-plug via on electromigration lifetime of metal interconnect w型插头通孔对金属互连电迁移寿命的影响
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854308
Q. Guo, K. Lo, I. Manna, S. Lim, X. Zeng, J. Cai
{"title":"Effect of W-plug via on electromigration lifetime of metal interconnect","authors":"Q. Guo, K. Lo, I. Manna, S. Lim, X. Zeng, J. Cai","doi":"10.1109/IITC.2000.854308","DOIUrl":"https://doi.org/10.1109/IITC.2000.854308","url":null,"abstract":"The effect of W-plug via on electromigration (EM) lifetime of the metal interconnects with bamboo structure and single/multiple vias has been systematically investigated by using high resolution resistance measurement (HRRM). It is found that the vias added in the structure significantly change its resistance degradation profile. W-plug vias not only cause discontinuity at the interface between metal and W-plug, but also make the metal stripe near W-plug via to be more vulnerable to electromigration, further reducing EM lifetime of metal stripe. This finding raises doubt about the assumption that adding multiple vias will proportionately prolong interconnect lifetime in a circuit design.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130706887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CVD Cu technology development for advanced Cu interconnect applications CVD铜技术的发展为先进的铜互连应用
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854337
Cheng-Hong Lee, K. Shen, T. Ku, C. Luo, Chia-Chun Tao, Hung-Wen Chou, C. Hsia
{"title":"CVD Cu technology development for advanced Cu interconnect applications","authors":"Cheng-Hong Lee, K. Shen, T. Ku, C. Luo, Chia-Chun Tao, Hung-Wen Chou, C. Hsia","doi":"10.1109/IITC.2000.854337","DOIUrl":"https://doi.org/10.1109/IITC.2000.854337","url":null,"abstract":"An advanced chemical vapor deposition Cu technology has been developed for 0.13 /spl mu/m Cu interconnect generation and beyond. Aggressive Cu via filling capability was successfully proved by CVD direct fill or CVD/ECD integration for via CD<0.1 /spl mu/m with AR>10. High via chain (20 K) yield and low resistance (<0.9/spl Omega//via) of 0.28 /spl mu/m borderless via were also achieved. Via filling and integration related issues including adhesion, texture, and CMP compatibility were also studied and resolved. Excellent filling capability, adequate adhesion and good [111] texture of the proposed CVD Cu based process exhibit superior extendibility toward sub-0.13 /spl mu/m technology node.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"746 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133691930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Development of a random-walk algorithm for IC-interconnect analysis: 2D TE benchmarks, materially homogeneous domains 用于ic互连分析的随机漫步算法的发展:2D TE基准，材料均匀域
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854314
K. Chatterjee, R. Iverson, Y. Le Coz
{"title":"Development of a random-walk algorithm for IC-interconnect analysis: 2D TE benchmarks, materially homogeneous domains","authors":"K. Chatterjee, R. Iverson, Y. Le Coz","doi":"10.1109/IITC.2000.854314","DOIUrl":"https://doi.org/10.1109/IITC.2000.854314","url":null,"abstract":"Fundamentally, the electrical properties of advanced multi-level IC interconnects must be described with Maxwell's equations. As an initial step towards developing an efficient methodology for electromagnetic analysis of IC interconnects, we have defined an entirely new numerical floating RW (Random-Walk) algorithm. The algorithm describes TE-mode (Transverse Electric) propagation within materially homogeneous 2D domains. The major difficulty of deriving simple, analytical surface Green's functions has been resolved by means of iterative perturbation theory. Square-domain insulator and conductor benchmark test problems yielded a mean absolute error of 0.004+0.0024i within a computed (normalized) solution range [0.0,1.0-0.3i]. Operation frequencies were 400 GHz and 1.0 GHz, for respective insulator and conductor problem sizes of 100 /spl mu/m and 10 /spl mu/m.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133935250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Microstructure characterization of metal interconnects and barrier layers: status and future 金属互连和阻挡层的微观结构表征:现状与未来
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854334
E. Zschech, P. Besser
{"title":"Microstructure characterization of metal interconnects and barrier layers: status and future","authors":"E. Zschech, P. Besser","doi":"10.1109/IITC.2000.854334","DOIUrl":"https://doi.org/10.1109/IITC.2000.854334","url":null,"abstract":"Metal interconnect and barrier characterization are challenged by reduced feature sizes, advanced materials, and new technologies. Microstructure characterization of new materials is done for thin films deposited on flat substrates and for on-chip interconnect structures. In this paper, both Al and Cu metallizations and respective barriers are discussed. Analytical requirements and advanced techniques for interconnect and barrier microstructure characterization will be covered. Specific topics will be composition and structure of interconnects and barriers, grain size, texture and stress in interconnect lines.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"420 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129313837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
CVD copper thin film deposition by using (1-pentene)Cu(I)(hfac) (1-戊烯)Cu(I)(hfac) CVD沉积铜薄膜
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854320
W. Zhuang, L. J. Charneski, D.R. Evans, S. Hsu
{"title":"CVD copper thin film deposition by using (1-pentene)Cu(I)(hfac)","authors":"W. Zhuang, L. J. Charneski, D.R. Evans, S. Hsu","doi":"10.1109/IITC.2000.854320","DOIUrl":"https://doi.org/10.1109/IITC.2000.854320","url":null,"abstract":"Pure copper thin films have been deposited on both TiN and TaN substrates via CVD process by using a new volatile copper precursor, (1-pentene)Cu(I)(hfac). The effect of CVD process conditions on film properties has been investigated. The copper nucleus size is about 200 /spl Aring/. The results indicate that both high deposition rate and low resistivity of copper thin films can be obtained by using (1-pentene)Cu(I)(hfac).","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130748795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An optical clock distribution network for gigascale integration 用于千兆级集成的光时钟分配网络
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854081
A. Mulé, S. M. Schultz, T. Gaylord, J. Meindl
{"title":"An optical clock distribution network for gigascale integration","authors":"A. Mulé, S. M. Schultz, T. Gaylord, J. Meindl","doi":"10.1109/IITC.2000.854081","DOIUrl":"https://doi.org/10.1109/IITC.2000.854081","url":null,"abstract":"A novel system-level model describing a printed wiring board-level, high-fanout, curved aperture optical waveguide H-tree network using volume grating focusing couplers is presented. The intra-chip optical network globally distributes an optical signal to monolithic CMOS receivers for local clock distribution. An estimation for the available optical output power as a function of distribution fanout is presented. Assuming -2 dB optical loss per y-junction, a distribution fanout of 256 can be achieved for an optical input power of 1.23 W.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114404816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Novel post electroplating in-situ rapid annealing process for advanced copper interconnect application 新型电镀后原位快速退火工艺的先进铜互连应用
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854323
M. Chen, H. Shin, R. Cheung, R. Morad, Y. Dordi, S. Rengarajan, S. Tsai
{"title":"Novel post electroplating in-situ rapid annealing process for advanced copper interconnect application","authors":"M. Chen, H. Shin, R. Cheung, R. Morad, Y. Dordi, S. Rengarajan, S. Tsai","doi":"10.1109/IITC.2000.854323","DOIUrl":"https://doi.org/10.1109/IITC.2000.854323","url":null,"abstract":"The room-temperature self-annealing behavior of electroplated (ECP) copper and its impact on device manufacturing has led to the investigation of a post ECP anneal process to stabilize copper film properties before CMP. A novel in-situ anneal chamber was developed to allow for rapid thermal annealing and cooling of ECP wafers on Applied Materials' Electra/sup TM/ Cu Integrated ECP System. This paper reports a detailed study of this process, including the impact of anneal temperature, time, and ambient on film sheet resistance, reflectivity, microstructure, hardness, as well as CMP polishing rate. Process repeatability results from an extended reliability test of the anneal chamber integrated with the Electra/sup TM/ Cu ECP System are also presented.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134471369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 7 level metallization with Cu damascene process using newly developed abrasive free polishing 采用新开发的无磨料抛光技术进行7级铜damascene金属化
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854343
H. Yamaguchi, N. Ohashi, T. Imai, K. Torii, J. Noguchi, T. Fujiwara, Tatsuyuki Saito, N. Owada, Y. Homma, Kondo Seiichi, K. Hinode
{"title":"A 7 level metallization with Cu damascene process using newly developed abrasive free polishing","authors":"H. Yamaguchi, N. Ohashi, T. Imai, K. Torii, J. Noguchi, T. Fujiwara, Tatsuyuki Saito, N. Owada, Y. Homma, Kondo Seiichi, K. Hinode","doi":"10.1109/IITC.2000.854343","DOIUrl":"https://doi.org/10.1109/IITC.2000.854343","url":null,"abstract":"A 7 level metallization including 4 levels of Cu metallization by the damascene technique is successfully developed using newly developed abrasive free polishing (AFP). This new AFP process reduced erosion and dishing, defect density, and improved TDDB lifetime of dielectric layers. We also improved corrosion resistance for Cu wiring. This process was used to fabricate a metallization structure of a new-cache memory chip consisting of 9-Mb 0.6-ns SRAMs and 200-K 25 ps ECL gate arrays. And this Cu metallization suppresses parasitic capacitance of interconnects and reduces clock wiring delay by 30%.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134107638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Thickness measurement for Cu and Ta thin films using optoacoustics 利用光声学测量Cu和Ta薄膜的厚度
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854317
M. Gostein, T. Bailey, I. Emesh, A. Diebold, A. Maznev, M. Banet, M. Joffe, R. Sacco
{"title":"Thickness measurement for Cu and Ta thin films using optoacoustics","authors":"M. Gostein, T. Bailey, I. Emesh, A. Diebold, A. Maznev, M. Banet, M. Joffe, R. Sacco","doi":"10.1109/IITC.2000.854317","DOIUrl":"https://doi.org/10.1109/IITC.2000.854317","url":null,"abstract":"New all-optical, nondestructive metrology instruments for metal film thickness measurement have been developed using the opto-acoustic technique impulsive stimulated thermal scattering (ISTS). The technique uses lasers to initiate and detect acoustic waves in the sample film. In this study, a commercial ISTS-based instrument is evaluated for measuring Cu and Ta thin films, and the results are compared with 4-point probe, SEM, TEM, and GIXR. We also show that ISTS can be used in conjunction with 4-point-probe to determine resistivity for thin PVD Cu films.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123629714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A copper drift-model for the low-/spl kappa/ polymer DVS-BCB 低/spl kappa/聚合物DVS-BCB的铜漂移模型
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854328
T. Hoernig, K. Melzer, U. Schubert, H. Geisler, J.W. Barthar
{"title":"A copper drift-model for the low-/spl kappa/ polymer DVS-BCB","authors":"T. Hoernig, K. Melzer, U. Schubert, H. Geisler, J.W. Barthar","doi":"10.1109/IITC.2000.854328","DOIUrl":"https://doi.org/10.1109/IITC.2000.854328","url":null,"abstract":"To prove the reliability of DVS-BCB (Benzocyclobutene) as an interlevel-dielectric in copper-metallization-systems we investigated the extreme low copper drift rate in this spin-on-polymer. BTS-Sequences (B_ias-T_emperature S_tress) were applied to accelerate the copper drift in the polymer. Using experimentally obtained data, an equation was created to compute the copper drift rate in the DVS-BCB as a function of the applied voltage and the temperature of the polymer. The copper drift rate in the DVS-BCB, Metal-Insulator-Substrat-structures (MIS) were determined by Capacitance-Voltage-measurements (CV). The results obtained by this method are supported by a Secondary ion Mass Spectroscopy-analysis (SIMS). A linear relationship between the logarithmic copper drift rate as a function of the applied voltage and the temperature of the polymer was determined. The experimental data used to establish the equation of the drift rate covers temperatures and electrical conditions used in integrated circuits under operation.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133709597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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