R. Goldblatt, B. Agarwala, M. B. Anand, E. Barth, G. Biery, Z. Chen, S. Cohen, J. B. Connolly, A. Cowley, T. Dalton, S.K. Das, C. Davis, A. Deutsch, C. Dewan, D. Edelstein, P.A. Emmi, C. G. Faltermeier, J. Fitzsimmons, J. Hedrick, J. Heidenreich, C. Hu, J. Hummel, P. Jones, E. Kaltalioglu, B.E. Kastenmeier, M. Krishnan, W.F. Landers, E. Liniger, J. Liu, N. Lustig, S. Malhotra, D. Manger, V. McGahay, R. Mih, H. Nye, S. Purushothaman, H. Rathore, S. Seo, T. Shaw, A. Simon, T. Spooner, M. Stetter, R. Wachnik, J. Ryan
{"title":"A high performance 0.13 /spl mu/m copper BEOL technology with low-k dielectric","authors":"R. Goldblatt, B. Agarwala, M. B. Anand, E. Barth, G. Biery, Z. Chen, S. Cohen, J. B. Connolly, A. Cowley, T. Dalton, S.K. Das, C. Davis, A. Deutsch, C. Dewan, D. Edelstein, P.A. Emmi, C. G. Faltermeier, J. Fitzsimmons, J. Hedrick, J. Heidenreich, C. Hu, J. Hummel, P. Jones, E. Kaltalioglu, B.E. Kastenmeier, M. Krishnan, W.F. Landers, E. Liniger, J. Liu, N. Lustig, S. Malhotra, D. Manger, V. McGahay, R. Mih, H. Nye, S. Purushothaman, H. Rathore, S. Seo, T. Shaw, A. Simon, T. Spooner, M. Stetter, R. Wachnik, J. Ryan","doi":"10.1109/IITC.2000.854342","DOIUrl":"https://doi.org/10.1109/IITC.2000.854342","url":null,"abstract":"The integration of dual damascene copper with low-k dielectric at the 0.13 /spl mu/m technology node is described. Up to five levels of copper wiring at three different metal pitches is provided in a spin-on organic inter metal dielectric (SiLK/sup TM/ semiconductor dielectric. The Dow Chemical Co.). Additional global wiring levels in fluorosilicate glass (FSG) at two different relaxed metal pitches result in a total of up to eight levels of hierarchical wiring for enhanced BEOL performance. Successful integration was achieved while maintaining reliability standards. Development of new advanced unit processes was required to meet the challenges presented by this work. Patterning and passivation methodologies are discussed. A key feature of the integration scheme and material set reported is the resulting reduction in complexity compared to other proposed low-k integration alternatives for the current generation.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115963818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Maisonobe, A. Ermolieff, P. Holliger, F. Laugier, G. Passemard
{"title":"Effect of fluorinated plasma on SiLK during mineral hard masks etching","authors":"J. Maisonobe, A. Ermolieff, P. Holliger, F. Laugier, G. Passemard","doi":"10.1109/IITC.2000.854281","DOIUrl":"https://doi.org/10.1109/IITC.2000.854281","url":null,"abstract":"This paper concerns the integration of low-k dielectric SiLK as interconnect insulator with copper metallization. It describes more particularly the impact of hard mask etching on SiLK. It was verified that fluorine based plasma transforms surface of SiLK into fluorinated polymer with interesting properties: organic solvent solutions do not penetrate this layer. However, during the etching step, it was observed that fluorine could physically diffuse into the SiLK volume. This fluorine can be easily removed using a basic aqueous solution.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115836712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Physical modeling of rinsing and cleaning of submicron trenches","authors":"Hong Lin, A. Busnaina, I. Suni","doi":"10.1109/IITC.2000.854278","DOIUrl":"https://doi.org/10.1109/IITC.2000.854278","url":null,"abstract":"Cleaning of surfaces and submicron deep trenches is a tremendous challenge in semiconductor manufacturing. In this work, the rinsing of blanket and patterned wafers using pulsating flow are studied using physical numerical modeling. Preliminary results on blanket wafers cleaning process show good agreement with numerical and experimental results of literatures. Preliminary results for blanket and patterned wafers show that oscillating flow rinse is more efficient than steady flow rinse, and the optimum frequency of the oscillating flow is a function of the size of the trench.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131450812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K.A. Ashtiani, E. Klawuhn, D. Hayden, M. ow, K. B. Levy, M. Danek
{"title":"A new hollow-cathode magnetron source for 0.10 /spl mu/m copper applications","authors":"K.A. Ashtiani, E. Klawuhn, D. Hayden, M. ow, K. B. Levy, M. Danek","doi":"10.1109/IITC.2000.854274","DOIUrl":"https://doi.org/10.1109/IITC.2000.854274","url":null,"abstract":"A new design Hollow-Cathode Magnetron (HCM) source was evaluated for 0.10 /spl mu/m copper (Cu) seed deposition applications. The new source included: (i) an external Dual Coil electromagnet for plasma confinement and metal ion flux control, and (ii) an optimized DC magnetron for high plasma density operation and improved target erosion. With the modified source, highly uniform deposition of copper seed(/spl sim/2%, 1/spl sigma/) was achieved on 200 mm wafers minimizing the center-to-edge variability in subsequent electrochemical copper fill (electrofill). In addition, the high plasma density operation significantly improved conformality of the seed deposition allowing reduction of the seed field thickness from 1500 /spl Aring/ to /spl sim/800 /spl Aring/ while achieving void free electrofill of 0.10-0.13 /spl mu/m test structures.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121681581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Ultra-low dielectric constant low density material (k=2.2) for Cu damascene","authors":"Y.Y. Cheng, L. Chao, S. Jang, C. Yu, M. Liang","doi":"10.1109/IITC.2000.854312","DOIUrl":"https://doi.org/10.1109/IITC.2000.854312","url":null,"abstract":"We have examined film properties of ultra-low dielectric constant low-density spin on glass with a dielectric constant of 2.2 (SOG-2.2). SOG-2.2 can stand higher shear strength and demonstrates better adhesion with PE-SiON than PE-SiN in scratch test. However, SOG-2.2 is damaged by conventional O2 plasma for photoresist stripping and also by wet processes for polymer removal. Using N2/H2 plasma for resist stripping, the damage can be minimized and moisture adsorption is significantly reduced, as evident in FTIR. In this work, SOG-2.2/Cu single damascene has been developed which demonstrates line-to-line capacitance reduction of 50%, compared with USG/Cu single damascene. Though there is leakage current in 0.23 /spl mu/m narrow spacing Cu line, TEM examination suggests that no Cu diffusion in low density SOG-2.2 inter-metal dielectric.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123208676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ki-Chul Park, Seungman Choi, Sun-jung Lee, K. Chang, Hyeon-deok Lee, Ho-Kyu Kang, Sang-In Lee
{"title":"Process integration of CVD Cu as a seed layer for Cu electroplating and a plug-fill application","authors":"Ki-Chul Park, Seungman Choi, Sun-jung Lee, K. Chang, Hyeon-deok Lee, Ho-Kyu Kang, Sang-In Lee","doi":"10.1109/IITC.2000.854276","DOIUrl":"https://doi.org/10.1109/IITC.2000.854276","url":null,"abstract":"CVD Cu film has been evaluated as a seed layer for Cu electroplating and a plug-fill application for back-end Cu metallization in 0.18 /spl mu/m technologies. Excellent step coverage and via plug-fill with CVD Cu were routinely obtained. CVD Cu film showed the enhanced seed layer performance compared to an ionized PVD Cu seed layer. It was found that only 40 /spl Aring/ PVD Cu interlayer between the TaN and CVD Cu layer is enough to obtain low via contact resistance. The scheme of the CVD Cu seed formation followed by Cu electroplating showed approximately 20% lower via resistance as compared to that of the CVD Cu plug-fill followed by Cu electroplating.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125257340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shawming Ma, R. Parker, R. Kavari, I. Leal, D. Boyers, J. Cremer
{"title":"An evaluation of the HotOzone/sup TM/ process: a new post etch resist and residue removal process","authors":"Shawming Ma, R. Parker, R. Kavari, I. Leal, D. Boyers, J. Cremer","doi":"10.1109/IITC.2000.854277","DOIUrl":"https://doi.org/10.1109/IITC.2000.854277","url":null,"abstract":"The HotOzone/sup TM/ process, a new ozone-water cleaning process for post-contact/via oxide etch or post-metal etch resist or residue removal, is evaluated. Test structures, using 0.35 /spl mu/m technology with I-line resist or 0.18 /spl mu/m technology with DUV resist, are fabricated on 150 mm wafers and then etched. In the first series the structures are not ashed before being subjected to the HotOzone/sup TM/ cleaning process. In the second series the structures are oxygen plasma ashed before being subjected to the HotOzone/sup TM/ cleaning process. Cross-section SEM photographs provide a preliminary assessment of the cleaning performance and corrosion performance of the new process implemented in a single wafer processing configuration with a cleaning time of 1.5 minutes or 3.0 minutes. This new process has demonstrated the potential to replace both the traditional oxygen plasma ashing and the post etch solvent clean processes for the post metal etch cleaning.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130237603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Sankaran, W. Harris, G. Nuesca, E. Shaffer, S.J. Hiartin, R. Geer
{"title":"Development of TiSiN diffusion barriers for Cu/SiLK metallization schemes","authors":"S. Sankaran, W. Harris, G. Nuesca, E. Shaffer, S.J. Hiartin, R. Geer","doi":"10.1109/IITC.2000.854275","DOIUrl":"https://doi.org/10.1109/IITC.2000.854275","url":null,"abstract":"Diffusion barrier optimization and compatibility studies were undertaken with respect to the integration of Cu/TiSiN stacks on SiLK low-k dielectric films. First-pass testing optimized TiSiN film composition and evaluated process compatibility with SiLK. TiSiN/SiO/sub 2/ stacks were used for baseline comparisons. Second-pass testing evaluated thermal stability of TiSiN/Cu/TiSiN/SiLK stacks against Cu diffusion and the stability of the TiSiN/SiLK interface. At temperatures up to 450/spl deg/C no variations in stack composition or interfacial morphology were evidenced.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121771377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Ronse, M. Maenhoudt, I. Pollentier, V. Wiaux, H. Struyf, M. Lepage, S. Vanhaelemeersch
{"title":"Lithography as a critical step for low-k dual damascene: from 248 nm to 193 nm","authors":"K. Ronse, M. Maenhoudt, I. Pollentier, V. Wiaux, H. Struyf, M. Lepage, S. Vanhaelemeersch","doi":"10.1109/IITC.2000.854290","DOIUrl":"https://doi.org/10.1109/IITC.2000.854290","url":null,"abstract":"Optical lithography is continuously pushed to its limits for volume manufacturing of integrated circuits. With the implementation of low-k dielectrics in the back-end-of-line processes, the optical properties of the dielectric stack have drastically changed. Also the transition from the conventional AlCu dry-etch scheme to several potential damascene integration schemes has significant impact on the lithography process and should be taken into account. Usually front-end-of-line development is considered as the driving force for lithography. However back-end lithography has become as challenging recently. In this paper, the various issues for back-end damascene lithography processes for the 0.13 um technology node will be outlined. The IMEC strategy for back-end-of-line lithography solutions will be outlined, for both 248 nm and 193 nm lithography.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116559724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Gandikota, A. Duboust, S. Neo, Liang-Yuh Chen, R. Cheung, D. Carl
{"title":"Extension of copper plating to 0.13 /spl mu/m nodes by pulse-modulated plating","authors":"S. Gandikota, A. Duboust, S. Neo, Liang-Yuh Chen, R. Cheung, D. Carl","doi":"10.1109/IITC.2000.854336","DOIUrl":"https://doi.org/10.1109/IITC.2000.854336","url":null,"abstract":"The electro-chemical deposition of copper can carried out by normal DC plating or using pulse plating approach. The superfill for gap fill can be achieved using either of these approaches-DC plating or pulse plating. The pulse plating approach has been observed to show advantages of greater tolerance to seed layer morphology besides controlled planarity, with no major detrimental effects on electrical yield or other film properties.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115967550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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