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Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)最新文献

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Electron spin resonance (ESR) characterization of defects in low-k dielectrics-temperature effect 电子自旋共振(ESR)表征低k介电体的温度效应缺陷
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854316
P. Turek, M. Bernard, N. Lardon, J. Maisonobe, G. Passemard
{"title":"Electron spin resonance (ESR) characterization of defects in low-k dielectrics-temperature effect","authors":"P. Turek, M. Bernard, N. Lardon, J. Maisonobe, G. Passemard","doi":"10.1109/IITC.2000.854316","DOIUrl":"https://doi.org/10.1109/IITC.2000.854316","url":null,"abstract":"The electron spin resonance (ESR) technique has been used for the detection and the study of paramagnetic defects in various low-k dielectrics. Whereas the studied organic polymers (SiLK(R), FLARE(R)) exhibit an ESR response as previously reported, no defects could be detected in the silicon based organo-mineral materials (MSQ, Black Diamond(R), Xerogel). A peculiar behavior is evidenced for the observed defects: (i) reversible variation of the defect concentration at air exposure/vacuum cycling, (ii) curing effect during annealing cycles.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"13 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114000770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The effect of residual tensile stress on electromigration lifetime of metal lines passivated by various oxides 残余拉应力对各种氧化物钝化金属线电迁移寿命的影响
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854326
Young-pil Kim, D. Kwon, Han-mei Choi, Young-wook Park, Sang-In Lee
{"title":"The effect of residual tensile stress on electromigration lifetime of metal lines passivated by various oxides","authors":"Young-pil Kim, D. Kwon, Han-mei Choi, Young-wook Park, Sang-In Lee","doi":"10.1109/IITC.2000.854326","DOIUrl":"https://doi.org/10.1109/IITC.2000.854326","url":null,"abstract":"Residual stress of metal interconnects passivated by four different oxides was precisely measured by X-ray diffraction method, and the effect of this stress on electromigration (EM) lifetime of the Al-Cu lines was investigated. The EM lifetime was not a monotonous function of the residual stress; instead, it increased with the stress at low stress region, but decreased at the higher stress region. The stress of 200-250 MPa, which is the mid-value between compressive and tensile yield strength of the Al-Cu lines, provided the maximum EM lifetime. This result gives an experimental support to a theoretical calculation on the stress evolution due to EM and a guideline to maximize the EM lifetime for applications.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121461968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reliability of dual damascene Cu metallization 双大马士革铜金属化的可靠性
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854329
M. Tsai, W. Tsai, S. Shue, C. Yu, M. Liang
{"title":"Reliability of dual damascene Cu metallization","authors":"M. Tsai, W. Tsai, S. Shue, C. Yu, M. Liang","doi":"10.1109/IITC.2000.854329","DOIUrl":"https://doi.org/10.1109/IITC.2000.854329","url":null,"abstract":"The electromigration (EM) and bias temperature stress (BTS) performances of Cu metallization in dual damascene structure were examined. The experimental results show that Cu has more than one order of magnitude EM lifetime relative to Al alloy. The activation energy of electromigration of Cu trench is 0.9 eV. The failure sites of Cu dual damascene process after EM stress testing are mainly in the bottom of cathode site's vias. Via electromigration can be improved up to one order magnitude by optimizing several processes such as PR stripping, pad structure, etc. BTS study results indicate that the activation energy of Cu ion drift leakage is around 1.1 to 1.4 eV. The interface of capping SiN and SiO/sub 2/ was found to be the major copper diffusion path. Lifetime extrapolated from the empirical data indicates that the device can sustain longer than 1000 years under normal operation condition.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114581429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Application of high pressure process into Cu/low-k technologies 高压工艺在铜/低钾工艺中的应用
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854295
K. Suzuki, T. Fujikawa, N. Kawakami
{"title":"Application of high pressure process into Cu/low-k technologies","authors":"K. Suzuki, T. Fujikawa, N. Kawakami","doi":"10.1109/IITC.2000.854295","DOIUrl":"https://doi.org/10.1109/IITC.2000.854295","url":null,"abstract":"High-pressure processing in the range of 16-120 MPa has been introduced to Cu/low-k interconnect technologies as a new generation. Hot isostatic pressing (HIP) was applied to the formation of Cu plugs with a high aspect ratio. A new finding related to a combination with electroplated Cu is also discussed. A supercritical CO/sub 2/ fluid was applied to a formation of low-k porous silica films as a means of capillary-force-free drying. A low dielectric constant, as low as 1.1, was achieved by using this technique. It is demonstrated that high-pressure processing has several attractive advantages for semiconductor processing.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124290389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Technology challenges for communications systems chips 通信系统芯片的技术挑战
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854079
M. Pinto
{"title":"Technology challenges for communications systems chips","authors":"M. Pinto","doi":"10.1109/IITC.2000.854079","DOIUrl":"https://doi.org/10.1109/IITC.2000.854079","url":null,"abstract":"In the era of 0.25 /spl mu/m and finer feature sizes, the IC industry has seen the advent of true systems chips (SoCs) where traditionally disparate functions-e.g., processors, logic, programmable elements, analog, RF, memory-are integrated monolithically to perform an applications level task. In addition to traditional VLSI scaling issues, SoCs present many special and sometimes unique technology challenges. This contribution focuses on those related to process technologies with a special focus on communications applications arguably the new driver of the IC industry.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"29 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123262059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparison of key performance metrics in two- and three-dimensional integrated circuits 二维和三维集成电路中关键性能指标的比较
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854268
A. Rahman, A. Fan, R. Reif
{"title":"Comparison of key performance metrics in two- and three-dimensional integrated circuits","authors":"A. Rahman, A. Fan, R. Reif","doi":"10.1109/IITC.2000.854268","DOIUrl":"https://doi.org/10.1109/IITC.2000.854268","url":null,"abstract":"In this paper some key performance metrics in two-dimensional (2-D) and three-dimensional (3-D) integrated circuits (IC) are estimated for scaled technologies from 250-nm to 50-nm technology nodes using a system-level modeling approach. Considering a microprocessor as an example, projections are made for performance metrics such as clock frequency, chip area, interconnect delay and repeater's number for 2-D and 3-D implementation.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124674471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Ultralow k SiO/sub 2/ thin films with nano-voids by gas-evaporation technique 利用气体蒸发技术制备具有纳米孔洞的超低k SiO/sub /薄膜
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854305
S. Nozaki, S. Banerjee, K. Uchida, H. Ono, H. Morisaki
{"title":"Ultralow k SiO/sub 2/ thin films with nano-voids by gas-evaporation technique","authors":"S. Nozaki, S. Banerjee, K. Uchida, H. Ono, H. Morisaki","doi":"10.1109/IITC.2000.854305","DOIUrl":"https://doi.org/10.1109/IITC.2000.854305","url":null,"abstract":"We have developed the gas evaporation technique to deposit ultralow-k (as low as 1.7) SiO/sub 2/ thin films with nanometer-size voids. In the technique silicon (Si) in a boat was evaporated in argon gas containing a small amount of oxygen. Although the film contains many nanometer-size voids, it is tolerant of moisture and does not show a change in the dielectric constant or the resistance with time. The SiO/sub 2/ film deposited by the gas evaporation technique is a good candidate for a low-k dielectric in the future Si VLSI.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133030929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The evaluation of the diffusion barrier performance of reactively sputtered TaN/sub x/ layers for copper metallization 铜金属化反应溅射TaN/sub x/层扩散阻挡性能的评价
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854322
J.C. Lin, C.S. Liu, S. Shue, C. Yu, M. Liang
{"title":"The evaluation of the diffusion barrier performance of reactively sputtered TaN/sub x/ layers for copper metallization","authors":"J.C. Lin, C.S. Liu, S. Shue, C. Yu, M. Liang","doi":"10.1109/IITC.2000.854322","DOIUrl":"https://doi.org/10.1109/IITC.2000.854322","url":null,"abstract":"Ta-based Cu diffusion barrier properties were widely studied. This work demonstrates that grain boundary diffusivity of Cu diffusion in various TaN/sub x/ (x=0/spl sim/0.62) thin films can be extracted from the copper concentration profile, based on the Whipple analysis of grain boundary diffusion, after annealing the samples at fixed temperatures between 200 and 500/spl deg/C. We used the grain boundary diffusivity to predict the penetration depth (2/spl radic/Dt) of Cu in Ta and TaN/sub x/ films at fixed temperatures 250 and 400/spl deg/C. Cu/TaN/sub x/(45 A)/N/sup +/P junction diode leakage, SIMS and XSEM analysis results indicated that the Whipple model correlates well with experimental results.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128869310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Generic models for interconnect delay across arbitrary wire-tree networks 跨任意线树网络互连延迟的一般模型
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854302
A. Bhavnagarwala, A. Kapoor, J. Meindl
{"title":"Generic models for interconnect delay across arbitrary wire-tree networks","authors":"A. Bhavnagarwala, A. Kapoor, J. Meindl","doi":"10.1109/IITC.2000.854302","DOIUrl":"https://doi.org/10.1109/IITC.2000.854302","url":null,"abstract":"New, generic and compact closed-form expressions for distributed wire-tree delay dependence on input ramp time, tree topology and wire geometries are reported. In agreement to within 5% of HSPICE simulations, these expressions permit rapid, accurate and early estimates of interconnect delay as well as variations in interconnect delay due to variations in interconnect process parameters across arbitrary distributed wire-tree networks.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121227420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Cleaning process strategies compatible with low-k dielectric and copper: state of the art, evolution and perspectives 与低钾电介质和铜兼容的清洗工艺策略:现状、演变和观点
Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) Pub Date : 2000-06-05 DOI: 10.1109/IITC.2000.854339
D. Louis, A. Beverina, C. Arvet, E. Lajoinie, C. Peyne, D. Holmes, D. Maloney, S. Lee, W.M. Lee
{"title":"Cleaning process strategies compatible with low-k dielectric and copper: state of the art, evolution and perspectives","authors":"D. Louis, A. Beverina, C. Arvet, E. Lajoinie, C. Peyne, D. Holmes, D. Maloney, S. Lee, W.M. Lee","doi":"10.1109/IITC.2000.854339","DOIUrl":"https://doi.org/10.1109/IITC.2000.854339","url":null,"abstract":"This work presents an analysis of interconnect cleaning for low-k/copper integration. Analytical and electrical data are combined to understand the mechanisms and efficacy of various available cleaning chemistries in the presence of Cu and organic, Si-based, and hybrid dielectrics.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122995887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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