H. Yamaguchi, N. Ohashi, T. Imai, K. Torii, J. Noguchi, T. Fujiwara, Tatsuyuki Saito, N. Owada, Y. Homma, Kondo Seiichi, K. Hinode
{"title":"采用新开发的无磨料抛光技术进行7级铜damascene金属化","authors":"H. Yamaguchi, N. Ohashi, T. Imai, K. Torii, J. Noguchi, T. Fujiwara, Tatsuyuki Saito, N. Owada, Y. Homma, Kondo Seiichi, K. Hinode","doi":"10.1109/IITC.2000.854343","DOIUrl":null,"url":null,"abstract":"A 7 level metallization including 4 levels of Cu metallization by the damascene technique is successfully developed using newly developed abrasive free polishing (AFP). This new AFP process reduced erosion and dishing, defect density, and improved TDDB lifetime of dielectric layers. We also improved corrosion resistance for Cu wiring. This process was used to fabricate a metallization structure of a new-cache memory chip consisting of 9-Mb 0.6-ns SRAMs and 200-K 25 ps ECL gate arrays. And this Cu metallization suppresses parasitic capacitance of interconnects and reduces clock wiring delay by 30%.","PeriodicalId":287825,"journal":{"name":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A 7 level metallization with Cu damascene process using newly developed abrasive free polishing\",\"authors\":\"H. Yamaguchi, N. Ohashi, T. Imai, K. Torii, J. Noguchi, T. Fujiwara, Tatsuyuki Saito, N. Owada, Y. Homma, Kondo Seiichi, K. Hinode\",\"doi\":\"10.1109/IITC.2000.854343\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 7 level metallization including 4 levels of Cu metallization by the damascene technique is successfully developed using newly developed abrasive free polishing (AFP). This new AFP process reduced erosion and dishing, defect density, and improved TDDB lifetime of dielectric layers. We also improved corrosion resistance for Cu wiring. This process was used to fabricate a metallization structure of a new-cache memory chip consisting of 9-Mb 0.6-ns SRAMs and 200-K 25 ps ECL gate arrays. And this Cu metallization suppresses parasitic capacitance of interconnects and reduces clock wiring delay by 30%.\",\"PeriodicalId\":287825,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2000.854343\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2000.854343","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
摘要
采用新开发的无磨料抛光(AFP)技术,成功地进行了含4个铜层的damascene 7级金属化。这种新的AFP工艺减少了介质层的侵蚀和碟形,缺陷密度,并提高了TDDB寿命。我们还提高了铜导线的耐腐蚀性。利用该工艺制备了由9 mb 0.6 ns sram和200 k 25 ps ECL门阵列组成的新型高速缓存芯片的金属化结构。铜金属化抑制了互连的寄生电容,使时钟布线延迟降低了30%。
A 7 level metallization with Cu damascene process using newly developed abrasive free polishing
A 7 level metallization including 4 levels of Cu metallization by the damascene technique is successfully developed using newly developed abrasive free polishing (AFP). This new AFP process reduced erosion and dishing, defect density, and improved TDDB lifetime of dielectric layers. We also improved corrosion resistance for Cu wiring. This process was used to fabricate a metallization structure of a new-cache memory chip consisting of 9-Mb 0.6-ns SRAMs and 200-K 25 ps ECL gate arrays. And this Cu metallization suppresses parasitic capacitance of interconnects and reduces clock wiring delay by 30%.