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2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)最新文献

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An Ultra-Low Power Temperature Sensor Based on Relaxation Oscillator in Standard CMOS 基于标准CMOS弛豫振荡器的超低功耗温度传感器
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-06 DOI: 10.1109/EDSSC.2018.8487078
Wendi Yang, Hanjun Jiang, Zhihua Wang, Wen Jia
{"title":"An Ultra-Low Power Temperature Sensor Based on Relaxation Oscillator in Standard CMOS","authors":"Wendi Yang, Hanjun Jiang, Zhihua Wang, Wen Jia","doi":"10.1109/EDSSC.2018.8487078","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487078","url":null,"abstract":"This work presents an ultra-low power CMOS temperature sensor in $0.13mu mathrm {m}$ standard CMOS process with an area of 0.0014mm2 and a power consumption of $0.15mu mathrm {W}$. CMOS transistors operating in subthreshold region generate the PTAT current, and a relaxation oscillator converts the current into frequency, which is digitalized by a following counter. The obtained oscillation frequency is nearly linear to the temperature, and a two-point calibration is applied to reduce the temperature spread in the range −0.27°C to 0.36°C.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132092785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Study of Self-Heating Effects in Silicon Nano-Sheet Transistors 纳米硅片晶体管的自热效应研究
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-06 DOI: 10.1109/EDSSC.2018.8487097
G. Chalia, R. Hegde
{"title":"Study of Self-Heating Effects in Silicon Nano-Sheet Transistors","authors":"G. Chalia, R. Hegde","doi":"10.1109/EDSSC.2018.8487097","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487097","url":null,"abstract":"The impact of Self-Heating Effect (SHE) on lateral Gate-All-Around (GAA) Nanosheet FET (NSFET) is numerically investigated by comparison of single and multi-channel NSFET with a single-channel FinFET. TCAD results show a 1.8% degradation in ON-current $(mathrm {{I} _{ON}})_{, }$for a NSFET in comparison to 2.4% for a FinFET with identical footprint and similar OFF-current $( mathrm {{I}_{OFF}})_{}$ values. Furthermore, by investigating the effect of geometry scaling on SHE, we conclude that NSFET exhibits better resilience to SHE in comparison to the FinFET.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117243704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Quadrature Injection Locked Frequency Tripler with Wide Tuning Range and Low Quadrature Error for MM-Wave Applications 用于毫米波应用的宽调谐范围和低正交误差的正交注入锁定三倍频器
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-06 DOI: 10.1109/EDSSC.2018.8487074
W. Zheng, Zhiyuan Chen, Yixiu Liao, Wei Wang, Jialiang Ye, B. Chi
{"title":"Quadrature Injection Locked Frequency Tripler with Wide Tuning Range and Low Quadrature Error for MM-Wave Applications","authors":"W. Zheng, Zhiyuan Chen, Yixiu Liao, Wei Wang, Jialiang Ye, B. Chi","doi":"10.1109/EDSSC.2018.8487074","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487074","url":null,"abstract":"This paper presents a quadrature injection locked oscillator as a frequency tripler to generate a 30GHz signal with 20% tuning range and low quadrature error by a phase calibration scheme. To enhance the locking range, a topology based upon dual injection to improve the injection efficiency is employed. The Quadrature Injection Locked Frequency Tripler (QILFT) implemented in 65nm CMOS process works at 27.3–33.3GHz with quadrature errors of 0.75° and 0.2dB, and consumes 21.6mW from a 1.2V supply.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129068048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The MOSFET performance degrading induced by electric heating coupling under electromagnetic pulse environment 电磁脉冲环境下电加热耦合对MOSFET性能的影响
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487129
Jinfu Lin, Hongxia Liu, Shulong Wang
{"title":"The MOSFET performance degrading induced by electric heating coupling under electromagnetic pulse environment","authors":"Jinfu Lin, Hongxia Liu, Shulong Wang","doi":"10.1109/EDSSC.2018.8487129","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487129","url":null,"abstract":"Strong electromagnetic pulses cause failure of the MOSFET mainly through electrical or thermal breakdown. Therefore, the study of the thermal distribution of MOSFET is of great significance. A three-dimensional(3D) MOSFET is established with appropriate parameters by device simulator software (Sentaurus). The damage effect and degrading mechanism of MOSFET induced by electromagnetic pulse (EMP) are analyzed in detail. The results show that with EMP injection the only hot spot is at the drain-substrate PN junction where it first reaches the melting point of silicon due to heat deposition. Meanwhile, electric field intensity and current density in this area are densely distributed. The device is thermally damaged due to electrical heating coupling and thus fails or burns out.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116782299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Simulation and mechanism analysis of MOSFET threshold voltage drift induced by manufacturing process 制造工艺诱发MOSFET阈值电压漂移的仿真及机理分析
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487079
Wei Gao, Pengfei Yin, Zehong Li, M. Ren, Jingping Zhang, Bo Zhang
{"title":"Simulation and mechanism analysis of MOSFET threshold voltage drift induced by manufacturing process","authors":"Wei Gao, Pengfei Yin, Zehong Li, M. Ren, Jingping Zhang, Bo Zhang","doi":"10.1109/EDSSC.2018.8487079","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487079","url":null,"abstract":"Three problems of threshold voltage(Vth) drift of Trench-MOSFET induced by manufacturing process are discussed. From the simulation results, it can be found that the N<sup>+</sup> source impurity compensation caused by P<sup>+</sup> ion implantation results in a low concentration N<sup>-</sup> region, which significantly increases the threshold voltage, and the width of N<sup>-</sup> region can cause the drift rate to reach 53.3%. The channeling effect of P<sup>+</sup> ion implantation also contributes to the threshold voltage drift up to 16.7% due to the increasing of doping concentration in p-body area. The temperature of the rapid-thermal-annealing (RTA) process of the source metal Ti/TiN layer influences the source electrode parasitic resistance, which makes the threshold voltage slightly drift up to 6.7%.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126050523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low Voltage Dual-Modulus Frequency Divider Based on Extended True Single-Phase Clock Logic 基于扩展真单相时钟逻辑的低压双模分频器
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487060
Wanlu Wang, S. Jia, Ziyi Wang, Tao Pan, Y. Wang
{"title":"Low Voltage Dual-Modulus Frequency Divider Based on Extended True Single-Phase Clock Logic","authors":"Wanlu Wang, S. Jia, Ziyi Wang, Tao Pan, Y. Wang","doi":"10.1109/EDSSC.2018.8487060","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487060","url":null,"abstract":"Two low voltage dual-modulus frequency divider based on extended true single-phase clock (E-TSPC) logic are proposed. By reducing the number of serial transistors from VDD to GND, the proposed designs can effectively work at low voltage. Simulation results in SMIC 40nm technology show that the presented design I has better power and speed performance with lower supply voltage. Compared to the referenced designs, the presented design II can work at the lowest supply voltage with little loss of performance.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114400871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Thermal Characteristics of ESD Diode in FDSOI Technologies FDSOI技术中ESD二极管的热特性
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487095
Zhaonian Yang, N. Yu, J. Liou
{"title":"Thermal Characteristics of ESD Diode in FDSOI Technologies","authors":"Zhaonian Yang, N. Yu, J. Liou","doi":"10.1109/EDSSC.2018.8487095","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487095","url":null,"abstract":"Electrostatic discharge (ESD) protection is very important for integrated circuits. In the fully depleted silicon on insulator (FDSOI) technology, the buried oxide (BOX) caused thermal degradation is one of the factors that degrade the intrinsic ESD robustness. In this work, the thermal characteristic of FDSOI ESD diode is investigated by TCAD simulations. The results show that the reduction in BOX thickness and material optimization can improve the heat dissipation and device’s ESD performance.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129834162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hydrogen Sensor Based on Pentacene Organic Thin-Film Transistor for Flexible Applications 基于并五苯有机薄膜晶体管的柔性氢传感器
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487082
Bochang Li, P. Lai, W. Tang
{"title":"Hydrogen Sensor Based on Pentacene Organic Thin-Film Transistor for Flexible Applications","authors":"Bochang Li, P. Lai, W. Tang","doi":"10.1109/EDSSC.2018.8487082","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487082","url":null,"abstract":"A flexible hydrogen gas sensor based on pentacene organic thin-film transistor (OTFT) using palladium (Pd) source and drain (S/D) electrodes as the sensing medium is prepared on adhesive vacuum tape. The sensor exhibits a clear, rapid and concentration-dependent response upon hydrogen exposure without the need of heating. In addition, in order to demonstrate the flexibility of the sensor, measurements on a curved surface are performed. The sensor, when attached to the curved surface, shows normal transistor characteristics, which essentially remains the same after one hour of tensile stress.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129869877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-Gain and Fast-Setting OTA for high Speed and high Resolution ADC 用于高速和高分辨率ADC的高增益和快速设置OTA
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487158
Yong Zhang, Ting Li, Zhengbo Huang, Yabo Ni, D. Fu
{"title":"High-Gain and Fast-Setting OTA for high Speed and high Resolution ADC","authors":"Yong Zhang, Ting Li, Zhengbo Huang, Yabo Ni, D. Fu","doi":"10.1109/EDSSC.2018.8487158","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487158","url":null,"abstract":"A two stage Gainboost OTA for high speed and high resolution Pipeline ADC is presented. Negative impedance compensation and Negative capacitance compensation are used to promote OTA DC gain and closeloop feedback coefficient; High resistances are in series connection between substrate of pmos and supply to decrease the output parasitic capacitor.Meanwhile, reset switchs are in parallel with high resistances to aviod voltage drift.The simulation of proposed circuit results in 83dB Loop DC gain, 4.3GHz Closeloop Bandwidth, and 63 degree phase margin.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124621093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Co-simulation Method of Power Amplifier for Reliability Optimization 功率放大器可靠性优化的联合仿真方法
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) Pub Date : 2018-06-01 DOI: 10.1109/EDSSC.2018.8487110
Yuanbo Ma, Bin Li, Zhaohui Wu, Haigang Wu, Zhijian Chen
{"title":"A Co-simulation Method of Power Amplifier for Reliability Optimization","authors":"Yuanbo Ma, Bin Li, Zhaohui Wu, Haigang Wu, Zhijian Chen","doi":"10.1109/EDSSC.2018.8487110","DOIUrl":"https://doi.org/10.1109/EDSSC.2018.8487110","url":null,"abstract":"An optimized design method for the reliability of power amplifier, based on the electric and thermal co-simulation is proposed. Different from traditional methods focused on device performance and separated from electrical parameters, it can build up a closed-loop feedback between temperature distribution of multi-heat source and the distortion of electrical parameters varied with temperature. Certified by the experimental results of CMOS and GaAs HBT process power amplifiers, the reliability can be optimized with minimizing area cost after several iterations.","PeriodicalId":279745,"journal":{"name":"2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123946980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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