基于扩展真单相时钟逻辑的低压双模分频器

Wanlu Wang, S. Jia, Ziyi Wang, Tao Pan, Y. Wang
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引用次数: 4

摘要

提出了两种基于扩展真单相时钟(E-TSPC)逻辑的低压双模分频器。通过减少从VDD到GND的串行晶体管数量,所提出的设计可以有效地在低电压下工作。在中芯国际40nm工艺下的仿真结果表明,该设计在较低的电源电压下具有较好的功耗和速度性能。与参考设计相比,本设计可以在最低的电源电压下工作,性能损失很小。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Low Voltage Dual-Modulus Frequency Divider Based on Extended True Single-Phase Clock Logic
Two low voltage dual-modulus frequency divider based on extended true single-phase clock (E-TSPC) logic are proposed. By reducing the number of serial transistors from VDD to GND, the proposed designs can effectively work at low voltage. Simulation results in SMIC 40nm technology show that the presented design I has better power and speed performance with lower supply voltage. Compared to the referenced designs, the presented design II can work at the lowest supply voltage with little loss of performance.
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