发布求助
文献互助 智能选刊 最新文献

2011 International Conference on Simulation of Semiconductor Processes and Devices最新文献

筛选
英文 中文
A Level Set simulator for nanooxidation using non-contact atomic force microscopy 使用非接触原子力显微镜进行纳米氧化的水平集模拟器
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035031
L. Filipovic, S. Selberherr
{"title":"A Level Set simulator for nanooxidation using non-contact atomic force microscopy","authors":"L. Filipovic, S. Selberherr","doi":"10.1109/SISPAD.2011.6035031","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035031","url":null,"abstract":"Atomic force microscopy (AFM) can be used as a lithographic technique capable of manufacturing nanometer-sized devices. A simulator for AFM, implemented in a Level Set environment, is presented. The simulator uses empirical models to deduce the shape of a desired nanodot based on the applied voltage, pulse time, and ambient humidity. The shape of an AFM nanowire depends on the same factors as the shape of the nanodot in addition to the wire's orientation with respect to the (010) direction. An advantage of the presented approach is the ease with which further processing steps can be simulated in the same environment. Sample oxide nanodots and nanowires are analyzed, showing the ability of the process to generate nanometer sized structures.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122508171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel simulation methodology for development of ESD primitives on a 0.18µm analog, mixed-signal high voltage process technology 一种新的模拟方法，用于在0.18 μ m模拟，混合信号高压工艺技术上开发ESD原语
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035080
F. Roger, J. Cambieri, R. Minixhofer
{"title":"A novel simulation methodology for development of ESD primitives on a 0.18µm analog, mixed-signal high voltage process technology","authors":"F. Roger, J. Cambieri, R. Minixhofer","doi":"10.1109/SISPAD.2011.6035080","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035080","url":null,"abstract":"This paper presents a full simulation methodology dedicated to the ESD primitive devices development in High Voltage technology. This workflow based on layout generation, 2D, 3D and mixed-mode TCAD simulations and SPICE simulations provide robust devices sustaining ESD stress tests.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123773233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhancement of the device characteristics for nanoscale charge trap flash memory devices utilizing a metal spacer layer 利用金属间隔层增强纳米级电荷阱闪存器件的器件特性
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035086
Hyun Woo Kim, J. H. You, D. Lee, Tae Whan Kim, Keun Woo Lee
{"title":"Enhancement of the device characteristics for nanoscale charge trap flash memory devices utilizing a metal spacer layer","authors":"Hyun Woo Kim, J. H. You, D. Lee, Tae Whan Kim, Keun Woo Lee","doi":"10.1109/SISPAD.2011.6035086","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035086","url":null,"abstract":"Nanoscale charge trap flash (CTF) memory devices with a metal spacer layer were designed to decrease the interference effect and to increase the fringing field effect and the coupling ratio. The optimum metal spacer depth of the memory devices was determined to enhance the device performance of the memory devices. The drain current and the threshold voltage shifts of the CTF memory devices were increased due to an increase in the fringing field and the coupling ratio resulting from the existence of the optimized metal spacer. The interference effect between neighboring cells was decreased due to the shielding of the electric field resulting from the existence of the metal spacer layer.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126418812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analytical model of drain current in nanowire MOSFETs including quantum confinement, band structure effects and quasi-ballistic transport: device to circuit performances analysis 包含量子约束、能带结构效应和准弹道输运的纳米线mosfet漏极电流分析模型:器件到电路性能分析
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035045
J. Dura, S. Martinie, D. Munteanu, F. Triozon, S. Barraud, Y. Niquet, J. Autran
{"title":"Analytical model of drain current in nanowire MOSFETs including quantum confinement, band structure effects and quasi-ballistic transport: device to circuit performances analysis","authors":"J. Dura, S. Martinie, D. Munteanu, F. Triozon, S. Barraud, Y. Niquet, J. Autran","doi":"10.1109/SISPAD.2011.6035045","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035045","url":null,"abstract":"This paper presents an analytical model of the drain current in nanowire MOSFETs (Fig. 1). This architecture is aimed for ultra-scaled devices up to technology nodes sub-11nm and uses silicon films of a few nanometers in thickness. At these dimensions, some emerging physical phenomena can no more be neglected: short-channel effects (SCE) and quasi-ballistic transport (both due to the channel length reduction) and quantum confinement and band structure effects (BSE), due to the strong silicon nanowire thinning. Our analytical model of the drain current includes all these physical phenomena. The proposed model is compared and validated on numerical simulations and experimental data. Finally, a study at the circuit level is performed to assess the impact of BSE and quasi-ballistic transport on the performances of small circuits such as CMOS inverters and ring oscillators based on ultimate nanowire MOSFETs.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"92 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126028694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A versatile finite volume simulator for the analysis of electronic properties of nanostructures 用于分析纳米结构电子特性的多功能有限体积模拟器
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035089
Z. Stanojević, M. Karner, K. Schnass, C. Kernstock, O. Baumgartner, H. Kosina
{"title":"A versatile finite volume simulator for the analysis of electronic properties of nanostructures","authors":"Z. Stanojević, M. Karner, K. Schnass, C. Kernstock, O. Baumgartner, H. Kosina","doi":"10.1109/SISPAD.2011.6035089","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035089","url":null,"abstract":"We present a novel semantic approach to modeling and simulation of nanoelectronic devices. The approach is based on a finite volume spatial discretization scheme. The scheme was adapted to accurately treat material anisotropy. It is thus capable of capturing orientation and strain effects both of which are prominent in the nanoscale regime. We also demonstrate the method's simplicity and power with a three-dimensional simulation study of a quantum dot using a six band k · p Hamiltonian for holes as model.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"113 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125855296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Simulation of channel electron mobility due to scattering with interfacial phonon-plasmon modes in silicon nanowire under the presence of high-k oxide and metal gate 在高k氧化物和金属栅存在下，硅纳米线中声子-等离子体模式散射导致通道电子迁移的模拟
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035043
K. Xiu
{"title":"Simulation of channel electron mobility due to scattering with interfacial phonon-plasmon modes in silicon nanowire under the presence of high-k oxide and metal gate","authors":"K. Xiu","doi":"10.1109/SISPAD.2011.6035043","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035043","url":null,"abstract":"The channel electron mobility of a 1D nanowire due to scattering with interfacial phonon-plasmon modes arising from the high-k dielectric material under the presence of polysilicon or metal gate is studied in this manuscript. We solved the dispersion relationship of the coupled modes and the accompanying effective scattering potential for carrier relaxation in the channel. The resulting mobility was calculated for a series of geometrical configurations with polysilicon/metal as the gate material. We found that for the polysilicon gate case the mechanism gives rise to a significantly low mobility in the low to mid electrical field range, and that wires with smaller diameter suffer more heavily. Our simulation also reveals that metal gate effectively mitigates the effect through the suppression of effective scattering field.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130344118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A parameterized SPICE macromodel of resistive random access memory and circuit demonstration 电阻式随机存储器的参数化SPICE宏模型及电路演示
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6034967
Huan-Lin Chang, Hsuan-Chih Li, C. Liu, F. Chen, M. Tsai
{"title":"A parameterized SPICE macromodel of resistive random access memory and circuit demonstration","authors":"Huan-Lin Chang, Hsuan-Chih Li, C. Liu, F. Chen, M. Tsai","doi":"10.1109/SISPAD.2011.6034967","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6034967","url":null,"abstract":"A parameterized SPICE macromodel of resistive random acess memory (RRAM) is demonstrated to simulate the memory chip. The two-terminal RRAM model has the features of (1) initial condition settings of high resistance state (HRS) or low resistance state (LRS) (2) a forming behavior option (3) DC/transient mode selection (4) unipolar/bipolar mode selection, and (5) multilevel cell (MLC) operation. The features have been verified in the simulation of memory peripheral circuits with good convergence.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131507464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Correlation between interface traps and random dopants in emerging MOSFETs 新兴mosfet中界面陷阱与随机掺杂物的相关性
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035026
Y. Chiu, Yiming Li, Hui-Wen Cheng
{"title":"Correlation between interface traps and random dopants in emerging MOSFETs","authors":"Y. Chiu, Yiming Li, Hui-Wen Cheng","doi":"10.1109/SISPAD.2011.6035026","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035026","url":null,"abstract":"In this work, we for the first time study the fluctuation and interaction between interface traps (ITs) and random dopants (RDs) of 16 nm MOSFETs. Totally random devices with 2D ITs at Si/high-к oxide interface and 3D RDs inside channel are simultaneously examined using an experimentally validated 3D device simulation. Pure random ITs at Si/high-к oxide interface will increase the threshold voltage (Vth) due to enlarge potential barrier resulting from accept-like ITs. However, the fluctuation of Vth (σVth) induced by ITs is smaller than the result of RDs. Considering the effect of ITs and RDs at the same time will result in coupled localized spikes of potential barrier and induced characteristics are much more correlated to each other which can not be estimated using adiabatic statistical sum calculation. Consequently, the effect of random ITs and RDs on device variability should be counted simultaneously for high-к / metal gate devices.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131344933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Characterization and modeling of self-heating effect on transient current overshoot in poly-Si TFTs fabricated on glass substrate 玻璃基板上制备的多晶硅tft中瞬态电流超调自热效应的表征与建模
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035073
T. Ota, H. Tsuji, Y. Kamakura, K. Taniguchi
{"title":"Characterization and modeling of self-heating effect on transient current overshoot in poly-Si TFTs fabricated on glass substrate","authors":"T. Ota, H. Tsuji, Y. Kamakura, K. Taniguchi","doi":"10.1109/SISPAD.2011.6035073","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035073","url":null,"abstract":"Characteristics of transient drain current overshoot in poly-Si TFTs are measured, and an equivalent thermal circuit model is proposed based on the experimental results. By changing the terminals on which a step voltage is applied, two main mechanisms causing the transient current, i.e., the electron trapping effect and the self-heating effect, can be separately evaluated. Using this new technique, we discuss the heat conduction mechanisms in TFTs responsible for describing the transient current overshoot component induced by the self-heating effect.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123869531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Tight-binding study of Γ-L bandstructure engineering for ballistic III–V nMOSFETs 弹道III-V型nmosfet Γ-L带结构工程紧密结合研究
2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI: 10.1109/SISPAD.2011.6035052
Ze Yuan, A. Nainani, X. Guan, H. Wong, K. Saraswat
{"title":"Tight-binding study of Γ-L bandstructure engineering for ballistic III–V nMOSFETs","authors":"Ze Yuan, A. Nainani, X. Guan, H. Wong, K. Saraswat","doi":"10.1109/SISPAD.2011.6035052","DOIUrl":"https://doi.org/10.1109/SISPAD.2011.6035052","url":null,"abstract":"A major concern for III–V nMOSFETs is the degradation of I<inf>ON</inf> due to low density of states and spillover of the charge from high-mobility Γ-valley to low-mobility L-valley at high sheet charge density. In this paper, we study these Γ-L bandstructure effects for ultrathin-body In<inf>x</inf>Ga<inf>1−x</inf>Sb nMOSFETs with varying stoichiometry using tight-binding and ballistic transport model.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123938060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信