Huan-Lin Chang, Hsuan-Chih Li, C. Liu, F. Chen, M. Tsai
{"title":"电阻式随机存储器的参数化SPICE宏模型及电路演示","authors":"Huan-Lin Chang, Hsuan-Chih Li, C. Liu, F. Chen, M. Tsai","doi":"10.1109/SISPAD.2011.6034967","DOIUrl":null,"url":null,"abstract":"A parameterized SPICE macromodel of resistive random acess memory (RRAM) is demonstrated to simulate the memory chip. The two-terminal RRAM model has the features of (1) initial condition settings of high resistance state (HRS) or low resistance state (LRS) (2) a forming behavior option (3) DC/transient mode selection (4) unipolar/bipolar mode selection, and (5) multilevel cell (MLC) operation. The features have been verified in the simulation of memory peripheral circuits with good convergence.","PeriodicalId":264913,"journal":{"name":"2011 International Conference on Simulation of Semiconductor Processes and Devices","volume":"78 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A parameterized SPICE macromodel of resistive random access memory and circuit demonstration\",\"authors\":\"Huan-Lin Chang, Hsuan-Chih Li, C. Liu, F. Chen, M. Tsai\",\"doi\":\"10.1109/SISPAD.2011.6034967\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A parameterized SPICE macromodel of resistive random acess memory (RRAM) is demonstrated to simulate the memory chip. The two-terminal RRAM model has the features of (1) initial condition settings of high resistance state (HRS) or low resistance state (LRS) (2) a forming behavior option (3) DC/transient mode selection (4) unipolar/bipolar mode selection, and (5) multilevel cell (MLC) operation. The features have been verified in the simulation of memory peripheral circuits with good convergence.\",\"PeriodicalId\":264913,\"journal\":{\"name\":\"2011 International Conference on Simulation of Semiconductor Processes and Devices\",\"volume\":\"78 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-10-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 International Conference on Simulation of Semiconductor Processes and Devices\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SISPAD.2011.6034967\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Conference on Simulation of Semiconductor Processes and Devices","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2011.6034967","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A parameterized SPICE macromodel of resistive random access memory and circuit demonstration
A parameterized SPICE macromodel of resistive random acess memory (RRAM) is demonstrated to simulate the memory chip. The two-terminal RRAM model has the features of (1) initial condition settings of high resistance state (HRS) or low resistance state (LRS) (2) a forming behavior option (3) DC/transient mode selection (4) unipolar/bipolar mode selection, and (5) multilevel cell (MLC) operation. The features have been verified in the simulation of memory peripheral circuits with good convergence.