A parameterized SPICE macromodel of resistive random access memory and circuit demonstration

Abstract

A parameterized SPICE macromodel of resistive random acess memory (RRAM) is demonstrated to simulate the memory chip. The two-terminal RRAM model has the features of (1) initial condition settings of high resistance state (HRS) or low resistance state (LRS) (2) a forming behavior option (3) DC/transient mode selection (4) unipolar/bipolar mode selection, and (5) multilevel cell (MLC) operation. The features have been verified in the simulation of memory peripheral circuits with good convergence.