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2020 IEEE Symposium on VLSI Circuits最新文献

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A 1 GS/s Reconfigurable BW 2nd-Order Noise-Shaping Hybrid Voltage-Time Two-Step ADC Achieving 170.9 dB FoMS 一种1gs /s可重构BW二阶噪声整形混合电压时间两步ADC，实现170.9 dB波形
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162805
Yifan Lyu, F. Tavernier
{"title":"A 1 GS/s Reconfigurable BW 2nd-Order Noise-Shaping Hybrid Voltage-Time Two-Step ADC Achieving 170.9 dB FoMS","authors":"Yifan Lyu, F. Tavernier","doi":"10.1109/VLSICircuits18222.2020.9162805","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162805","url":null,"abstract":"This paper presents a reconfigurable BW 2nd-order noise-shaping (NS) hybrid voltage-time ADC based on the two-step ADC structure. Composed by a SAR ADC in the 1st stage and a time-based-converter (TBC) in the 2nd stage, with a reconfigurable passive filter, it realizes a 2nd-order NS while simultaneously maintaining a simple and high-speed operation. Due to the delay introduced by the inter-stage residue amplifier (RA), one NS order is inherently provided by the pipelined architecture. Fabricated in 28 nm CMOS, the prototype chip operates at 1 GS/s while consuming 2.3 mW at 1 V. At an OSR of 4, the SNDR is 63.58 dB leading to a 170.9 dB FoMS. Thanks to the reconfigurable filter, the ADC is able to achieve 163.5 dB and 171.6 dB FoMs at OSR of 2 and 6, respectively.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128139985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 6.78 MHz Wireless Power Transfer System Enabling Perpendicular Wireless Powering with Efficiency Increase from 0.02% to 48.2% by Adaptive Magnetic Field Adder IC Integrating Shared Coupling Coefficient Sensor 采用自适应磁场加法器集成共享耦合系数传感器的6.78 MHz无线传输系统，实现垂直无线供电，效率从0.02%提高到48.2%
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162904
Hao Qiu, T. Sai, M. Takamiya
{"title":"A 6.78 MHz Wireless Power Transfer System Enabling Perpendicular Wireless Powering with Efficiency Increase from 0.02% to 48.2% by Adaptive Magnetic Field Adder IC Integrating Shared Coupling Coefficient Sensor","authors":"Hao Qiu, T. Sai, M. Takamiya","doi":"10.1109/VLSICircuits18222.2020.9162904","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162904","url":null,"abstract":"To achieve a misalignment-free wireless power transfer (WPT), an IC for an adaptive magnetic field adder (AMFA), where the magnetic fields from multiple transmitter (TX) coils are adaptively added based on the coupling coefficient (k) between each TX coil and the receiver (RX) coil, is realized for the first time. A 6.78 MHz AMFA IC fabricated in 1.8 V, 180 nm CMOS integrating four power amplifiers (PAs) and shared k sensor increases the perpendicular WPT efficiency from 0.02 % to 48.2 % with the load power of 458 mW.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125663047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Compact 14 GS/s 8-Bit Switched-Capacitor DAC in 16 nm FinFET CMOS 一个紧凑的14 GS/s 8位开关电容DAC在16纳米FinFET CMOS
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162776
P. Caragiulo, O. E. Mattia, A. Arbabian, B. Murmann
{"title":"A Compact 14 GS/s 8-Bit Switched-Capacitor DAC in 16 nm FinFET CMOS","authors":"P. Caragiulo, O. E. Mattia, A. Arbabian, B. Murmann","doi":"10.1109/VLSICircuits18222.2020.9162776","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162776","url":null,"abstract":"This paper presents a compact DAC for digital-intensive transmitter architectures. To minimize area and to leverage the strengths of FinFET CMOS, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad switched capacitors. The 14 GS/s 8-bit design occupies only 0.011 mm2 and supports up to 0.32 Vpp signal swing across its differential 100 Ω load. It achieves IM3 < −45.3 dBc across the first Nyquist zone while consuming 50 mW from a single 0.8 V supply.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132058632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm 一个3mm2的可编程贝叶斯推理加速器，用于无监督机器感知，使用并行吉布斯采样在16nm
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/vlsicircuits18222.2020.9162784
Glenn G. Ko, Yuji Chai, M. Donato, P. Whatmough, Thierry Tambe, Rob A. Rutenbar, D. Brooks, Gu-Yeon Wei
{"title":"A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm","authors":"Glenn G. Ko, Yuji Chai, M. Donato, P. Whatmough, Thierry Tambe, Rob A. Rutenbar, D. Brooks, Gu-Yeon Wei","doi":"10.1109/vlsicircuits18222.2020.9162784","DOIUrl":"https://doi.org/10.1109/vlsicircuits18222.2020.9162784","url":null,"abstract":"This paper describes a 16nm programmable accelerator for unsupervised probabilistic machine perception tasks that performs Bayesian inference on probabilistic models mapped onto a 2D Markov Random Field, using MCMC. Exploiting two degrees of parallelism, it performs Gibbs sampling inference at up to 1380× faster with 1965× less energy than an Arm Cortex-A53 on the same SoC, and 1.5× faster with 6.3× less energy than an embedded FPGA in the same technology. At 0.8V, it runs at 450MHz, producing 44.6 MSamples/s at 0.88 nJ/sample.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132566905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads 用于内存带宽有限的工作负载的2x -带宽突发6T-SRAM
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162815
C. Augustine, Somnath Paul, Turbo Majumder, J. Tschanz, M. Khellah, V. De
{"title":"2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads","authors":"C. Augustine, Somnath Paul, Turbo Majumder, J. Tschanz, M. Khellah, V. De","doi":"10.1109/VLSICircuits18222.2020.9162815","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162815","url":null,"abstract":"A 20KB 6T-SRAM array in 10nm CMOS demonstrates 2X higher read bandwidth in burst mode operation. The doubling of bandwidth is achieved with 51% higher energy efficiency than frequency doubling and 30% better area efficiency than doubling the number of banks.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115223053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS 617 TOPS/W全数字二进制神经网络加速器在10nm FinFET CMOS
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162949
Phil C. Knag, Gregory K. Chen, H. Sumbul, Raghavan Kumar, M. Anders, Himanshu Kaul, S. Hsu, A. Agarwal, Monodeep Kar, Seongjong Kim, R. Krishnamurthy
{"title":"A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS","authors":"Phil C. Knag, Gregory K. Chen, H. Sumbul, Raghavan Kumar, M. Anders, Himanshu Kaul, S. Hsu, A. Agarwal, Monodeep Kar, Seongjong Kim, R. Krishnamurthy","doi":"10.1109/VLSICircuits18222.2020.9162949","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162949","url":null,"abstract":"A 10nm digital Binary Neural Network (BNN) chip implements 1b activations and weights for compute density of 418TOPS/mm2 and memory density of 414KB/mm2. The chip achieves an energy efficiency of 617TOPS/W by leveraging Compute Near Memory (CNM), parallel inner product compute, and Near-Threshold Voltage (NTV) operation. The digital BNN design approaches the energy efficiency of analog in-memory techniques while also ensuring deterministic, scalable, and precise operation.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116486132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 4GHz 0.73psrms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC 带有抖动跟踪dll辅助DTC的4GHz 0.73 psms集成抖动pvt不敏感分数n子采样环锁相环
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162861
Jaehong Jung, Sangdon Jung, Kyungmin Lee, Jun-Hee Jung, Seungjin Kim, Byungki Han, Seunghyun Oh, Jongwoo Lee
{"title":"A 4GHz 0.73psrms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC","authors":"Jaehong Jung, Sangdon Jung, Kyungmin Lee, Jun-Hee Jung, Seungjin Kim, Byungki Han, Seunghyun Oh, Jongwoo Lee","doi":"10.1109/VLSICircuits18222.2020.9162861","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162861","url":null,"abstract":"This paper proposes a fractional-N sub-sampling ring PLL employing a jitter-tracking DLL-assisted DTC. The DTC achieves 0.49ps resolution and 0.98LSBrms INL with a dynamic range reduction through multi-phases of the DLL. In addition, an adaptive pulse-width control technique allows the loop BW to be insensitive to PVT, yielding <9.6% jitter variation. The proposed ring PLL fabricated in a 14nm FinFET CMOS process achieves 0.73psrms-integrated-jitter and 10.2mW power in fractional-N mode.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"46 15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124459346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW 基于PSD和BW去耦的降低kT/C噪声的SAR ADC
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162846
Zhelu Li, Arnab Dutta, Abhishek Mukherjee, Xiyuan Tang, Linxiao Shen, Lenian He, Nan Sun
{"title":"A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW","authors":"Zhelu Li, Arnab Dutta, Abhishek Mukherjee, Xiyuan Tang, Linxiao Shen, Lenian He, Nan Sun","doi":"10.1109/VLSICircuits18222.2020.9162846","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162846","url":null,"abstract":"This paper presents a SAR ADC with reduced front-end sampling kT/C noise. This is achieved by using an active sampling circuit with a specially designed 2-stage amplifier that decouples the tight relationship between the sampling noise power spectral density (PSD) and BW. A 12-bit 12-MS/s prototype ADC in 40nm CMOS achieves the sampling noise power reduction by 3.5 times. It permits the use of a small sampling capacitor of only 132 fF. This relaxes the requirement on the ADC input driver and reference buffer, which can lead to significant savings in power, area, and complexity on the system level.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128671968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 293/440 GHz Push-Push Double Feedback Oscillators with 5.0/−3.9 dBm Output Power and 2.9/0.6 % DC-to-RF Efficiency in 65 nm CMOS 293/440 GHz推推双反馈振荡器，输出功率5.0/−3.9 dBm, dc - rf效率2.9/ 0.6%
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162796
Dzuhri Radityo Utomo, Dae-Woong Park, Byeonghun Yun, Sang-Gug Lee
{"title":"A 293/440 GHz Push-Push Double Feedback Oscillators with 5.0/−3.9 dBm Output Power and 2.9/0.6 % DC-to-RF Efficiency in 65 nm CMOS","authors":"Dzuhri Radityo Utomo, Dae-Woong Park, Byeonghun Yun, Sang-Gug Lee","doi":"10.1109/VLSICircuits18222.2020.9162796","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162796","url":null,"abstract":"This work proposes a push-push double feedback oscillator (DFBO) topology, which is able to reduce the parasitic capacitance of the transistor, and satisfy the condition for maximum power at fundamental (fo) and 2nd harmonic (2fo) frequencies simultaneously, thus maximizing the oscillator output power. Oscillators adopting the proposed topology are implemented in a 65-nm CMOS, and the measurements show the maximum output powers of 5.0 and −3.9 dBm with maximum DC-to-RF efficiencies of 2.94 and 0.58 % at operating frequencies of 293 and 440 GHz, respectively.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127105707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 4.45 ms Low-Latency 3D Point-Cloud-Based Neural Network Processor for Hand Pose Estimation in Immersive Wearable Devices 用于沉浸式可穿戴设备手部姿势估计的4.45 ms低延迟3D点云神经网络处理器
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/vlsicircuits18222.2020.9162895
Dongseok Im, Sanghoon Kang, Donghyeon Han, Sungpill Choi, H. Yoo
{"title":"A 4.45 ms Low-Latency 3D Point-Cloud-Based Neural Network Processor for Hand Pose Estimation in Immersive Wearable Devices","authors":"Dongseok Im, Sanghoon Kang, Donghyeon Han, Sungpill Choi, H. Yoo","doi":"10.1109/vlsicircuits18222.2020.9162895","DOIUrl":"https://doi.org/10.1109/vlsicircuits18222.2020.9162895","url":null,"abstract":"A 3D point-cloud-based neural network (PNN) processor is proposed for the low-latency hand pose estimation (HPE) system. The processor adopts the heterogeneous core architecture to accelerate both convolution layers (CLs) and sampling-grouping layers (SGLs). The proposed window-based sampling-grouping (WSG) directly samples and groups the 3D points from the streaming depth image to boost up the throughput by ×2.34. Furthermore, the max pooling prediction (MPP) predicts the 64- and 128-to-1 max pooling outputs with ×1.31 throughput enhancement. In addition, the tiled data based MPP (TMPP) performs the MPP with the tiled input data to hide the latency of the MPP. As a result, the processor achieves 4.45 ms latency on the HPE system.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130678487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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