Zhelu Li, Arnab Dutta, Abhishek Mukherjee, Xiyuan Tang, Linxiao Shen, Lenian He, Nan Sun
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引用次数: 6
摘要
本文提出了一种降低前端采样kT/C噪声的SAR ADC。这是通过使用带有专门设计的2级放大器的有源采样电路来实现的，该电路可以解耦采样噪声功率谱密度(PSD)和BW之间的紧密关系。采用40nm CMOS的12位12 ms /s原型ADC，采样噪声功耗降低了3.5倍。它允许使用一个只有132 fF的小采样电容。这降低了对ADC输入驱动器和参考缓冲器的要求，从而可以在系统级别上显著节省功耗、面积和复杂性。
A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW
This paper presents a SAR ADC with reduced front-end sampling kT/C noise. This is achieved by using an active sampling circuit with a specially designed 2-stage amplifier that decouples the tight relationship between the sampling noise power spectral density (PSD) and BW. A 12-bit 12-MS/s prototype ADC in 40nm CMOS achieves the sampling noise power reduction by 3.5 times. It permits the use of a small sampling capacitor of only 132 fF. This relaxes the requirement on the ADC input driver and reference buffer, which can lead to significant savings in power, area, and complexity on the system level.
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