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2020 IEEE Symposium on VLSI Circuits最新文献

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A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation 一种支持双极化MIMO的28 ghz CMOS相控阵波束形成器
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162882
Jian Pang, Zheng Li, Xueting Luo, Joshua Alvin, Rattanan Saengchan, A. Fadila, K. Yanagisawa, Yi Zhang, Zixin Chen, Zhongliang Huang, Xiaofan Gu, Rui Wu, Yun Wang, Dongwon You, Bangan Liu, Zheng Sun, Yucheng Zhang, Hongye Huang, Naoki Oshima, K. Motoi, S. Hori, K. Kunihiro, T. Kaneko, A. Shirane, K. Okada
{"title":"A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation","authors":"Jian Pang, Zheng Li, Xueting Luo, Joshua Alvin, Rattanan Saengchan, A. Fadila, K. Yanagisawa, Yi Zhang, Zixin Chen, Zhongliang Huang, Xiaofan Gu, Rui Wu, Yun Wang, Dongwon You, Bangan Liu, Zheng Sun, Yucheng Zhang, Hongye Huang, Naoki Oshima, K. Motoi, S. Hori, K. Kunihiro, T. Kaneko, A. Shirane, K. Okada","doi":"10.1109/VLSICircuits18222.2020.9162882","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162882","url":null,"abstract":"This paper introduces a CMOS 28-GHz phased-array beamformer chip supporting dual-polarized MIMO (DP-MIMO) operation. A cross-pol. leakage cancellation technique is implemented for improving the degraded cross-pol. isolation caused by the antennas and the propagation. More than 40-dB cross-pol. isolation is maintained along the TX array to the RX array. This work also adopts a compact neutralized bidirectional architecture to minimize the chip manufacturing cost. The bi-directional PA-LNA realizes a peak PAE of 33.1% in PA mode and an NF of 5.4dB in LNA mode. With the improved cross-pol. isolation, 2×2 DP-MIMO communication with two 5G NR OFDMA-mode streams in 256QAM is achieved in the OTA measurement. The corresponding TX-to-RX EVM is 3.3%. The power consumptions for each antenna path are 181mW in TX mode and 88mW in RX mode.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117261639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Luncheon Talk 午餐谈话
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/vlsicircuits18222.2020.9162780
Do You
{"title":"Luncheon Talk","authors":"Do You","doi":"10.1109/vlsicircuits18222.2020.9162780","DOIUrl":"https://doi.org/10.1109/vlsicircuits18222.2020.9162780","url":null,"abstract":"Speaker: Andrew “bunnie” Huang Abstract: We normally think of design verification as an activity that wraps up once a product goes to production. However, in the face of increasingly adversarial supply chains, it can no longer be taken for granted that the product’s intention matches the product received by the end customer. In this talk we will briefly overview the adversarial landscape of the supply chain, and then switch gears to discuss a range of potential solutions.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121059541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage 双端口无场SOT-MRAM在55纳米CMOS技术和1.2 v电源电压下实现90 mhz读和60 mhz写操作
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/vlsicircuits18222.2020.9162774
M. Natsui, A. Tamakoshi, H. Honjo, Toshinari Watanabe, T. Nasuno, Chaoliang Zhang, T. Tanigawa, H. Inoue, M. Niwa, T. Yoshiduka, Y. Noguchi, M. Yasuhira, Yitao Ma, Hui Shen, S. Fukami, Hideo Sato, S. Ikeda, H. Ohno, T. Endoh, T. Hanyu
{"title":"Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage","authors":"M. Natsui, A. Tamakoshi, H. Honjo, Toshinari Watanabe, T. Nasuno, Chaoliang Zhang, T. Tanigawa, H. Inoue, M. Niwa, T. Yoshiduka, Y. Noguchi, M. Yasuhira, Yitao Ma, Hui Shen, S. Fukami, Hideo Sato, S. Ikeda, H. Ohno, T. Endoh, T. Hanyu","doi":"10.1109/vlsicircuits18222.2020.9162774","DOIUrl":"https://doi.org/10.1109/vlsicircuits18222.2020.9162774","url":null,"abstract":"We demonstrate an SOT-MRAM, a nonvolatile memory using spin-orbit-torque (SOT) devices that have a read-disturbance-free characteristic. The SOT-MRAM fabricated by a 55-nm CMOS process achieves 60-MHz write and 90-MHz read operations with 1.2-V supply voltage under a magnetic-field-free condition. The SOT-MRAM is also implemented in a dual-port configuration utilizing three-terminal structure of the device, which realizes a wide bandwidth applicable to high-speed applications.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123276885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 247 and 272 GHz Two-Stage Regenerative Amplifiers in 65 nm CMOS with 18 and 15 dB Gain Based on Double-Gmax Gain Boosting Technique 基于双gmax增益提升技术的247ghz和272ghz 65 nm CMOS两级增益增益18和15 dB放大器
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162862
Dae-Woong Park, Dzuhri Radityo Utomo, Jong-Phil Hong, K. Vaesen, P. Wambacq, Sang-Gug Lee
{"title":"A 247 and 272 GHz Two-Stage Regenerative Amplifiers in 65 nm CMOS with 18 and 15 dB Gain Based on Double-Gmax Gain Boosting Technique","authors":"Dae-Woong Park, Dzuhri Radityo Utomo, Jong-Phil Hong, K. Vaesen, P. Wambacq, Sang-Gug Lee","doi":"10.1109/VLSICircuits18222.2020.9162862","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162862","url":null,"abstract":"This work proposes the concept of double-Gmax (Gmax : maximum achievable gain) core based regenerative amplifier which, in principle, breaks the gain barrier of Gmax (the highest gain that can be obtained from a single transistor) at the frequencies below the maximum oscillation frequency of the transistor. Regenerative amplifiers adopting the proposed double-Gmax core are implemented in a 65 nm CMOS technology and measurements show the peak gain of 18 and 15 dB, 9 and 7.5 dB per stage, at 247 and 272 GHz, respectively.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116144839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Performance-Flexible Energy-Optimized Automotive-Grade Cortex-R4F SoC through Combined AVS/ABB/Bias-in-Memory-Array Closed-Loop Regulation in 28nm FD-SOI 基于AVS/ABB/偏置存储器阵列闭环调节的汽车级Cortex-R4F SoC
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162790
R. Gomez, E. Bano, A. Cathelin, S. Clerc
{"title":"A Performance-Flexible Energy-Optimized Automotive-Grade Cortex-R4F SoC through Combined AVS/ABB/Bias-in-Memory-Array Closed-Loop Regulation in 28nm FD-SOI","authors":"R. Gomez, E. Bano, A. Cathelin, S. Clerc","doi":"10.1109/VLSICircuits18222.2020.9162790","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162790","url":null,"abstract":"We propose an automotive-grade ARM¯ Cortex¯-R4F core SoC in 28nm FD-SOI that optimizes its energy across 11X frequency-wide Operational Performance Points (OPPs) by combining Adaptive Voltage Scaling (AVS), Adaptive Body-Biasing (ABB) and Bias-in-Memory-Array (BiMA); with a 3mV/bit Tunable Replica Circuit (TRC) for safety, embedded power regulation and compensation. The reported techniques respectively improve by, 21X performance, 120mV lower VMIN , and 8X lifetime, the Low-Power, Mid-, and High-Performance OPPs. Results have been measured at extreme conditions, covering SS/TT/FF process, 0.5/1.2V, −40/150°C, and EOL aging.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117291388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Panel Sessions [3 abstracts] 小组讨论[3个摘要]
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/vlsicircuits18222.2020.9162823
{"title":"Panel Sessions [3 abstracts]","authors":"","doi":"10.1109/vlsicircuits18222.2020.9162823","DOIUrl":"https://doi.org/10.1109/vlsicircuits18222.2020.9162823","url":null,"abstract":"","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129483970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 29.2 Mb/mm2 Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit 29.2 Mb/mm2超高密度SRAM宏，采用7nm FinFET技术，双边缘驱动字线/位线和写/读辅助电路
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/vlsicircuits18222.2020.9162985
Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, M. Morimoto, M. Yabuuchi, Y. Ishii, S. Tanaka
{"title":"A 29.2 Mb/mm2 Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit","authors":"Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, M. Morimoto, M. Yabuuchi, Y. Ishii, S. Tanaka","doi":"10.1109/vlsicircuits18222.2020.9162985","DOIUrl":"https://doi.org/10.1109/vlsicircuits18222.2020.9162985","url":null,"abstract":"A 29.2Mb/mm2 ultra high density SRAM macro has been proposed using 7-nm CMOS FinFET technology. The SRAM macro has only one SRAM cell array despite of the huge array of 512 rows × 512 columns. The circuitry of dual-edge driver for such long wordline and bitline in such huge array are newly proposed. The SRAM macro using proposed circuit was designed, and a test chip was fabricated using 7-nm CMOS FinFET technology. The minimum operation voltage is improved 170 mV by the new circuits.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129229823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring 785nW多模态(V/I/R)传感器接口IC用于臭氧污染物传感和相关心血管疾病监测
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/vlsicircuits18222.2020.9162901
Peng Wang, Rishika Agarwala, Henry L. Bishop, Anjana Dissanayake, B. Calhoun
{"title":"A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring","authors":"Peng Wang, Rishika Agarwala, Henry L. Bishop, Anjana Dissanayake, B. Calhoun","doi":"10.1109/vlsicircuits18222.2020.9162901","DOIUrl":"https://doi.org/10.1109/vlsicircuits18222.2020.9162901","url":null,"abstract":"This paper presents a 785nW multimodal sensor interface IC enabling ozone pollutant sensing and correlated cardiovascular disease (CVD) monitoring based on electrocardiography (ECG) and photoplethysmography (PPG). The interface IC consists of a 165nW voltage-mode ECG channel, a 532nW current-mode PPG channel, a 75.6nW resistive ozone channel, and 12.6nW peripheral circuits, all at 0.6V. A 4MΩ-gain regulated cascode transimpedance amplifier (RGC-TIA) with a hybrid DC offset current cancellation (DCOC) loop reduces the PPG readout power by 37×, compared to state-of-the-art PPG sensor interfaces. Fabricated in 65nm CMOS, the proposed IC is tested with a custom digital readout IC. The full system power consumption with an LED is 11.5μW, which is 54× less than prior ozone/CVD joint-monitoring sensor interface systems.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123922551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An RF Transceiver with Full Digital Interface Supporting 5G New Radio FR1 with 3.84Gbps DL/1.92Gbps UL and Dual-Band GNSS in 14nm FinFET CMOS 具有全数字接口的射频收发器，支持5G新无线电FR1，具有3.84Gbps DL/1.92Gbps UL和双带GNSS，采用14nm FinFET CMOS
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162850
Sangwoo Han, Jaehyuk Jang, Jaeseung Lee, Daechul Jeong, Joonhee Lee, Jongsoo Lee, Chung Lau, Juyoung Han, Sung-Jun Lee, Jeongyeol Bae, Ikkyun Cho, Sang-Yun Lee, Shinwoong Kim, Jae Hoon Lee, Yanghoon Lee, Jaehong Jung, Junho Huh, Jongwoo Lee, T. B. Cho, Inyup Kang
{"title":"An RF Transceiver with Full Digital Interface Supporting 5G New Radio FR1 with 3.84Gbps DL/1.92Gbps UL and Dual-Band GNSS in 14nm FinFET CMOS","authors":"Sangwoo Han, Jaehyuk Jang, Jaeseung Lee, Daechul Jeong, Joonhee Lee, Jongsoo Lee, Chung Lau, Juyoung Han, Sung-Jun Lee, Jeongyeol Bae, Ikkyun Cho, Sang-Yun Lee, Shinwoong Kim, Jae Hoon Lee, Yanghoon Lee, Jaehong Jung, Junho Huh, Jongwoo Lee, T. B. Cho, Inyup Kang","doi":"10.1109/VLSICircuits18222.2020.9162850","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162850","url":null,"abstract":"This paper presents an RF CMOS transceiver supporting all cellular protocols including 5G Frequency Range (FR) 1 with eighteen receiver pipelines and two chains of transmitters. To transfer data for all combinations of carrier aggregation (CA) and a dual-band quad-GNSS system efficiently to a modem, a fully-digital interface is implemented instead of a conventional analog interface, resulting in enhanced signal integrity and smaller PCB area. The digitally-intensive design of this work, implemented in 14nm CMOS process, boosts the performance of RF/analog circuits with various digital-aid calibrations.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114620734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency 具有动态电流转向的双轨混合模拟/数字LDO，可调高PSRR和高效率
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162880
Xiaosen Liu, H. Krishnamurthy, Claudia P. Barrera, Jing Han, R. Bhatla, Scott Chiu, K. Z. Ahmed, K. Ravichandran, J. Tschanz, V. De
{"title":"A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency","authors":"Xiaosen Liu, H. Krishnamurthy, Claudia P. Barrera, Jing Han, R. Bhatla, Scott Chiu, K. Z. Ahmed, K. Ravichandran, J. Tschanz, V. De","doi":"10.1109/VLSICircuits18222.2020.9162880","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162880","url":null,"abstract":"A dual-rail hybrid analog/digital LDO achieves both high efficiency and tunable high PSRR simultaneously using a dynamic current steering mechanism. Measurements on a 22nm CMOS test chip demonstrate up to −46dB PSRR and 89% efficiency across 0–80mA load from1.8V/1.05V dual-input rails.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"37 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124520289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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