Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, M. Morimoto, M. Yabuuchi, Y. Ishii, S. Tanaka
{"title":"29.2 Mb/mm2超高密度SRAM宏，采用7nm FinFET技术，双边缘驱动字线/位线和写/读辅助电路","authors":"Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, M. Morimoto, M. Yabuuchi, Y. Ishii, S. Tanaka","doi":"10.1109/vlsicircuits18222.2020.9162985","DOIUrl":null,"url":null,"abstract":"A 29.2Mb/mm2 ultra high density SRAM macro has been proposed using 7-nm CMOS FinFET technology. The SRAM macro has only one SRAM cell array despite of the huge array of 512 rows × 512 columns. The circuitry of dual-edge driver for such long wordline and bitline in such huge array are newly proposed. The SRAM macro using proposed circuit was designed, and a test chip was fabricated using 7-nm CMOS FinFET technology. The minimum operation voltage is improved 170 mV by the new circuits.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 29.2 Mb/mm2 Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit\",\"authors\":\"Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, M. Morimoto, M. Yabuuchi, Y. Ishii, S. Tanaka\",\"doi\":\"10.1109/vlsicircuits18222.2020.9162985\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 29.2Mb/mm2 ultra high density SRAM macro has been proposed using 7-nm CMOS FinFET technology. The SRAM macro has only one SRAM cell array despite of the huge array of 512 rows × 512 columns. The circuitry of dual-edge driver for such long wordline and bitline in such huge array are newly proposed. The SRAM macro using proposed circuit was designed, and a test chip was fabricated using 7-nm CMOS FinFET technology. The minimum operation voltage is improved 170 mV by the new circuits.\",\"PeriodicalId\":252787,\"journal\":{\"name\":\"2020 IEEE Symposium on VLSI Circuits\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vlsicircuits18222.2020.9162985\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsicircuits18222.2020.9162985","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 29.2 Mb/mm2 Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit
A 29.2Mb/mm2 ultra high density SRAM macro has been proposed using 7-nm CMOS FinFET technology. The SRAM macro has only one SRAM cell array despite of the huge array of 512 rows × 512 columns. The circuitry of dual-edge driver for such long wordline and bitline in such huge array are newly proposed. The SRAM macro using proposed circuit was designed, and a test chip was fabricated using 7-nm CMOS FinFET technology. The minimum operation voltage is improved 170 mV by the new circuits.
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