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2020 IEEE Symposium on VLSI Circuits最新文献

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A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface 用于高速存储器接口的28-mW 32gb /s/引脚16-QAM单端收发器
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162874
Jieqiong Du, Jia Zhou, Chia-Jen Liang, B. Hu, Yuan Du, Mau-Chung Frank Chang
{"title":"A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface","authors":"Jieqiong Du, Jia Zhou, Chia-Jen Liang, B. Hu, Yuan Du, Mau-Chung Frank Chang","doi":"10.1109/VLSICircuits18222.2020.9162874","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162874","url":null,"abstract":"A 32-Gb/s low-power single-ended 16-QAM transceiver using four signal levels is presented for high-speed memory interface. With four-bit per symbol, the transceiver increases the symbol period by 4× to enhance energy-efficiency by reducing the bandwidth requirement for most circuit blocks and mitigating equalization requirements. The transmitter achieves 16-QAM modulation by combining two QPSK modulators for linearity relaxation. Taking advantage of the DC-balanced 16-QAM signal, the receiver adopts a low-noise single-to-differential amplifier with a low-power DC feedback to recover the signal without requiring an external reference. The proposed transceiver achieves 0.875 pJ/bit at full rate while occupying 0.018 mm2 in 28-nm CMOS technology.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131408160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Domino Bootstrapping 12V GaN Driver for Driving an On-Chip 650V eGaN Power Switch for 96% High Efficiency 用于驱动片上650V GaN电源开关的多米诺自举12V GaN驱动器，效率高达96%
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162979
Hsuan-Yu Chen, Wei-Tin Lin, Cheng-Hsiang Liao, Zong-Yi Lin, Zhi-Qiang Zhang, Yu-Yung Kao, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
{"title":"A Domino Bootstrapping 12V GaN Driver for Driving an On-Chip 650V eGaN Power Switch for 96% High Efficiency","authors":"Hsuan-Yu Chen, Wei-Tin Lin, Cheng-Hsiang Liao, Zong-Yi Lin, Zhi-Qiang Zhang, Yu-Yung Kao, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai","doi":"10.1109/VLSICircuits18222.2020.9162979","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162979","url":null,"abstract":"The proposed monolithically integrated 12V Gallium Nitride (GaN) driver utilizes a domino bootstrapping technique to an on-chip 650V enhancement mode Gallium Nitride (eGaN) in a GaN process. The proposed self-biasing loop (SBL) reduces the quiescent current to 120μA and achieves 96% high efficiency. Furthermore, derivative-voltage divided by derivative-time (dV/dt) controller with a dual current supply (DCS) technique is proposed to modulate the slew rate of eGaN HEMT from 53.3V/ns to 12.5V/ns.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115907728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp 一个10.4mW 50MHz-BW 80dB-DR单运放三阶CTSDM，带有ab - ld合并集成商和3级运放
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162797
Kai Xing, Wei Wang, Yan Zhu, Chi-Hang Chan, R. Martins
{"title":"A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp","authors":"Kai Xing, Wei Wang, Yan Zhu, Chi-Hang Chan, R. Martins","doi":"10.1109/VLSICircuits18222.2020.9162797","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162797","url":null,"abstract":"This paper presents a wideband and energy-efficient single-loop 3rd order CTSDM enabled by an ELD-SAB-Merged integrator and a 3-stage opamp. We utilize only a single DAC and opamp to accomplish the ELD compensation in the SAB structure. While featuring a PSQ technique and a 1st order NS-SAR, the 28nm prototype achieves a 74.4dB SNDR in a 50MHz BW and consumes 10.4mW with 171.2dB FoMS.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116418915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor 7nm Hexagon™处理器的主动电压下降缓解系统
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162808
V. K. Kalyanam, E. Mahurin, K. Bowman, J. Abraham
{"title":"A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor","authors":"V. K. Kalyanam, E. Mahurin, K. Bowman, J. Abraham","doi":"10.1109/VLSICircuits18222.2020.9162808","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162808","url":null,"abstract":"A proactive clock-gating system (PCGS) in a 7nm Qualcomm<sup>¯</sup> Hexagon™ digital signal processor (DSP) predicts supply voltage (V<inf>DD</inf>) droops based on microarchitectural events and a power-delivery-network (PDN) model and adapts clock frequency (F<inf>CLK</inf>) to reduce the V<inf>DD</inf> droop. Silicon measurements demonstrate 10% higher F<inf>CLK</inf> or 5% lower V<inf>DD</inf>.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114743816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices 基于高效亚阈值乘子和片上混合信号训练的低功耗边缘器件混合信号时域生成对抗网络加速器
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/vlsicircuits18222.2020.9162829
Zhengyu Chen, Sihua Fu, Qiankai Cao, Jie Gu
{"title":"A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices","authors":"Zhengyu Chen, Sihua Fu, Qiankai Cao, Jie Gu","doi":"10.1109/vlsicircuits18222.2020.9162829","DOIUrl":"https://doi.org/10.1109/vlsicircuits18222.2020.9162829","url":null,"abstract":"This work presents a low-cost mixed-signal time-domain accelerator for generative adversarial network (GAN). A significant reduction in hardware cost was achieved through delicate architecture optimization for 8-bit GAN training on edge devices. An area efficient subthreshold time-domain multiplier was designed to eliminate excessive data conversion for mixed-signal computing enabling high throughput mixed-signal online training demonstrated in a 65nm CMOS test chip.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122557475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An Autonomous Reconfigurable Power Delivery Network (RPDN) for Many-Core SoCs Featuring Dynamic Current Steering 基于动态电流控制的多核soc自主可重构供电网络(RPDN)
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162827
Zakir K. Ahmed, H. Krishnamurthy, Sheldon Weng, Xiaosen Liu, C. Schaef, Nachiket V. Desai, K. Ravichandran, J. Tschanz, V. De
{"title":"An Autonomous Reconfigurable Power Delivery Network (RPDN) for Many-Core SoCs Featuring Dynamic Current Steering","authors":"Zakir K. Ahmed, H. Krishnamurthy, Sheldon Weng, Xiaosen Liu, C. Schaef, Nachiket V. Desai, K. Ravichandran, J. Tschanz, V. De","doi":"10.1109/VLSICircuits18222.2020.9162827","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162827","url":null,"abstract":"A 2-input/4-output autonomous RPDN in 14nm CMOS with dynamic current steering enables better core-count and FIVR scalability for many-core SoCs in scaled process nodes while improving the overall area efficiency of on-die power delivery/management circuits by 35%. The RPDN controller minimizes losses for a variety of operating conditions to improve overall energy efficiency in most runtime scenarios while complying with all local and global current limits.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117295290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS 用于10nm CMOS的高性能图形/AI处理器的低时钟功耗数字标准单元ip
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9163007
S. Hsu, A. Agarwal, S. Realov, M. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, H. Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, S. Mathew, Iqbal Rajwani, Satish Damaraju, R. Krishnamurthy, V. De
{"title":"Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS","authors":"S. Hsu, A. Agarwal, S. Realov, M. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, H. Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, S. Mathew, Iqbal Rajwani, Satish Damaraju, R. Krishnamurthy, V. De","doi":"10.1109/VLSICircuits18222.2020.9163007","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9163007","url":null,"abstract":"Low-clock-power digital standard cell IPs in 10nm CMOS, featuring low-power shared-clock (LPSC) flip-flops (FFs), LPSC back-to-back (B2B) FFs, and pass-gate (PG) integrated clock gates (ICGs), achieve up to 14%, 45%, and 14% measured clock energy improvements, respectively, by reducing the number of clocked devices over state-of-the-art conventional transmission-gate (TG) FF and AND ICG circuits. The LPSC FF achieves a mean worst-case black-hole-time (BHT) improvement of 17ps, while the PG ICG achieves a mean enable/disable setup time improvement of 16ps/15ps, compared to conventional circuits measured at 650mV, 25°C. Power analysis of a graphics processor block with these optimized IPs results in an overall 6% clock power reduction without frequency impact.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115559936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-Density and Large-Scale MEA System Featuring 236,880 Electrodes at 11.72μm Pitch for Neuronal Network Analysis 高密度大规模MEA系统，具有236,880个电极，间距为11.72μm，用于神经网络分析
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162947
Yuri Kato, Y. Matoba, K. Honda, Koji Ogawa, Kan Shimizu, Masataka Maehara, Atsushi Fujiwara, A. Odawara, Chigusa Yamane, N. Kimizuka, J. Ogi, T. Taura, I. Suzuki, Y. Oike
{"title":"High-Density and Large-Scale MEA System Featuring 236,880 Electrodes at 11.72μm Pitch for Neuronal Network Analysis","authors":"Yuri Kato, Y. Matoba, K. Honda, Koji Ogawa, Kan Shimizu, Masataka Maehara, Atsushi Fujiwara, A. Odawara, Chigusa Yamane, N. Kimizuka, J. Ogi, T. Taura, I. Suzuki, Y. Oike","doi":"10.1109/VLSICircuits18222.2020.9162947","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162947","url":null,"abstract":"Microelectrode arrays (MEAs) allow us to observe electrical activities from neurons at multiple sites. This paper presents a high-density microelectrode array (HD-MEA) for observing neuronal networks at a cellular level, featuring 236,880 electrodes at an 11.72 μm pitch and 33,840 readout channels with a noise level of 5.5 μVrms. The Peltier cooling system is integrated to maintain the temperature of the electrodes at approximately 37 °C. Moreover, electrical signals for the axonal propagation of rat neurons are successfully recorded.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115664848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An 8Ω, 1.4W, 0.0024% THD+N Class-D Audio Amplifier with Bridge-Tied Load Half-Side Switching Mode Achieving Low Standby Quiescent Current of 660μA 一种8Ω、1.4W、0.0024% THD+N、桥系负载半侧开关模式的d类音频放大器，待机静态电流低至660μA
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162781
Ji-Hun Lee, Gyeong-Gu Kang, Min-Woo Ko, G. Cho, Hyunsik Kim
{"title":"An 8Ω, 1.4W, 0.0024% THD+N Class-D Audio Amplifier with Bridge-Tied Load Half-Side Switching Mode Achieving Low Standby Quiescent Current of 660μA","authors":"Ji-Hun Lee, Gyeong-Gu Kang, Min-Woo Ko, G. Cho, Hyunsik Kim","doi":"10.1109/VLSICircuits18222.2020.9162781","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162781","url":null,"abstract":"In this paper, a Class-D audio amplifier (CDA) with bridge-tied load half-side switching (BTLHS) mode is presented. The BTLHS mode through a digital pulse width subtracter (DPWS) enables a low quiescent current (IQ) by suspending the output switching in idle condition while maintaining high linearity with seamless zero-crossings and mode change. The CDA achieves 0.0024% THD+N, IQ of 0.66mA, and 95% peak efficiency on an 8Ω-speaker. The chip was fabricated in a 0.18-μm CMOS process, and it occupies 0.83mm2.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123449376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 25×50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-Tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS 一个25×50Gb/s 2.22pJ/b NRZ RX双bank和3 tap推测DFE用于微处理器在7nm FinFET CMOS
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162821
Yang You, Glen A. Wiedemeier, Chad A. Marquart, Chris Steffen, Erik English, Dereje Yilma, Thomas Pham, V. Nammi, Jeffrey Okyere, Nathan Blanchard, A. Sutton, Ze Zhang, D. Friend, Diego Barba, Tyler Bohlke, Michael Spear, V. Raj, James Crugnale, D. Dreps, P. Francese, M. Kossel, T. Morf
{"title":"A 25×50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-Tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS","authors":"Yang You, Glen A. Wiedemeier, Chad A. Marquart, Chris Steffen, Erik English, Dereje Yilma, Thomas Pham, V. Nammi, Jeffrey Okyere, Nathan Blanchard, A. Sutton, Ze Zhang, D. Friend, Diego Barba, Tyler Bohlke, Michael Spear, V. Raj, James Crugnale, D. Dreps, P. Francese, M. Kossel, T. Morf","doi":"10.1109/VLSICircuits18222.2020.9162821","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162821","url":null,"abstract":"This work presents an NRZ receiver (RX) implementation for microprocessor application in 7nm FinFET CMOS technology. It covers data rate from 25 to 50Gb/s and features on-chip AC coupling to support a wide input common-mode range. The RX includes two identical banks with their own clock and data recovery (CDR) to dynamically tackle parameter drift over time. A quarter-rate 3-tap fully speculative decision feedback equalizer (DFE) opens eyes over channel with 30dB insertion loss. Current-mode logic (CML) based clock path boasts three degrees of freedom of phase adjustment and random jitter (RJ) attenuation to broaden the eyes. At 0.9V supply the energy efficiency is 2.22pJ/b with 28% eye opening (BER=10−12) at 50Gb/s with PRBS31 and channel loss of 20dB.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115244058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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