7nm Hexagon™处理器的主动电压下降缓解系统

2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI:10.1109/VLSICircuits18222.2020.9162808

V. K. Kalyanam, E. Mahurin, K. Bowman, J. Abraham

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引用次数: 7

摘要

采用7nm高通¯Hexagon™数字信号处理器(DSP)的主动时钟门控系统(PCGS)基于微架构事件和功率传输网络(PDN)模型预测电源电压(VDD)下降，并调整时钟频率(FCLK)以减少VDD下降。硅测量显示FCLK提高10%或VDD降低5%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor

A proactive clock-gating system (PCGS) in a 7nm Qualcomm^¯ Hexagon™ digital signal processor (DSP) predicts supply voltage (VDD) droops based on microarchitectural events and a power-delivery-network (PDN) model and adapts clock frequency (FCLK) to reduce the VDD droop. Silicon measurements demonstrate 10% higher FCLK or 5% lower VDD.

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2020 IEEE Symposium on VLSI Circuits

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