一个25×50Gb/s 2.22pJ/b NRZ RX双bank和3 tap推测DFE用于微处理器在7nm FinFET CMOS

2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI:10.1109/VLSICircuits18222.2020.9162821

Yang You, Glen A. Wiedemeier, Chad A. Marquart, Chris Steffen, Erik English, Dereje Yilma, Thomas Pham, V. Nammi, Jeffrey Okyere, Nathan Blanchard, A. Sutton, Ze Zhang, D. Friend, Diego Barba, Tyler Bohlke, Michael Spear, V. Raj, James Crugnale, D. Dreps, P. Francese, M. Kossel, T. Morf

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引用次数: 1

摘要

本工作提出了一种用于微处理器应用的NRZ接收器(RX)在7nm FinFET CMOS技术中的实现。它涵盖了从25到50Gb/s的数据速率，并具有片上交流耦合，以支持宽输入共模范围。RX包括两个相同的银行，它们有自己的时钟和数据恢复(CDR)，以动态处理参数随时间的漂移。四分之一速率三分接全推测决策反馈均衡器(DFE)在30dB插入损耗的信道上打开了眼睛。基于电流模式逻辑(CML)的时钟路径具有三个自由度的相位调整和随机抖动(RJ)衰减，以拓宽视野。在0.9V的电源下，能量效率为2.22pJ/b，睁眼率为28% (BER=10−12)，50Gb/s, PRBS31，信道损耗为20dB。

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A 25×50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-Tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS

This work presents an NRZ receiver (RX) implementation for microprocessor application in 7nm FinFET CMOS technology. It covers data rate from 25 to 50Gb/s and features on-chip AC coupling to support a wide input common-mode range. The RX includes two identical banks with their own clock and data recovery (CDR) to dynamically tackle parameter drift over time. A quarter-rate 3-tap fully speculative decision feedback equalizer (DFE) opens eyes over channel with 30dB insertion loss. Current-mode logic (CML) based clock path boasts three degrees of freedom of phase adjustment and random jitter (RJ) attenuation to broaden the eyes. At 0.9V supply the energy efficiency is 2.22pJ/b with 28% eye opening (BER=10−12) at 50Gb/s with PRBS31 and channel loss of 20dB.

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2020 IEEE Symposium on VLSI Circuits

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