A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor

Abstract

A proactive clock-gating system (PCGS) in a 7nm Qualcomm^¯ Hexagon™ digital signal processor (DSP) predicts supply voltage (VDD) droops based on microarchitectural events and a power-delivery-network (PDN) model and adapts clock frequency (FCLK) to reduce the VDD droop. Silicon measurements demonstrate 10% higher FCLK or 5% lower VDD.