一个10.4mW 50MHz-BW 80dB-DR单运放三阶CTSDM，带有ab - ld合并集成商和3级运放

2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI:10.1109/VLSICircuits18222.2020.9162797

Kai Xing, Wei Wang, Yan Zhu, Chi-Hang Chan, R. Martins

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引用次数: 5

摘要

本文提出了一种宽带、高能效的单回路三阶CTSDM，由一个eld - sabb合并集成器和一个3级运放实现。我们仅使用一个DAC和运放来完成SAB结构中的ELD补偿。28nm原型采用PSQ技术和一阶NS-SAR，在50MHz BW下实现74.4dB SNDR，在171.2dB FoMS下消耗10.4mW。

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A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp

This paper presents a wideband and energy-efficient single-loop 3rd order CTSDM enabled by an ELD-SAB-Merged integrator and a 3-stage opamp. We utilize only a single DAC and opamp to accomplish the ELD compensation in the SAB structure. While featuring a PSQ technique and a 1st order NS-SAR, the 28nm prototype achieves a 74.4dB SNDR in a 50MHz BW and consumes 10.4mW with 171.2dB FoMS.

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2020 IEEE Symposium on VLSI Circuits

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