A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface

Abstract

A 32-Gb/s low-power single-ended 16-QAM transceiver using four signal levels is presented for high-speed memory interface. With four-bit per symbol, the transceiver increases the symbol period by 4× to enhance energy-efficiency by reducing the bandwidth requirement for most circuit blocks and mitigating equalization requirements. The transmitter achieves 16-QAM modulation by combining two QPSK modulators for linearity relaxation. Taking advantage of the DC-balanced 16-QAM signal, the receiver adopts a low-noise single-to-differential amplifier with a low-power DC feedback to recover the signal without requiring an external reference. The proposed transceiver achieves 0.875 pJ/bit at full rate while occupying 0.018 mm2 in 28-nm CMOS technology.