S. Hsu, A. Agarwal, S. Realov, M. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, H. Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, S. Mathew, Iqbal Rajwani, Satish Damaraju, R. Krishnamurthy, V. De
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引用次数: 1
Abstract
Low-clock-power digital standard cell IPs in 10nm CMOS, featuring low-power shared-clock (LPSC) flip-flops (FFs), LPSC back-to-back (B2B) FFs, and pass-gate (PG) integrated clock gates (ICGs), achieve up to 14%, 45%, and 14% measured clock energy improvements, respectively, by reducing the number of clocked devices over state-of-the-art conventional transmission-gate (TG) FF and AND ICG circuits. The LPSC FF achieves a mean worst-case black-hole-time (BHT) improvement of 17ps, while the PG ICG achieves a mean enable/disable setup time improvement of 16ps/15ps, compared to conventional circuits measured at 650mV, 25°C. Power analysis of a graphics processor block with these optimized IPs results in an overall 6% clock power reduction without frequency impact.
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