A 4GHz 0.73psrms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC

Abstract

This paper proposes a fractional-N sub-sampling ring PLL employing a jitter-tracking DLL-assisted DTC. The DTC achieves 0.49ps resolution and 0.98LSBrms INL with a dynamic range reduction through multi-phases of the DLL. In addition, an adaptive pulse-width control technique allows the loop BW to be insensitive to PVT, yielding <9.6% jitter variation. The proposed ring PLL fabricated in a 14nm FinFET CMOS process achieves 0.73psrms-integrated-jitter and 10.2mW power in fractional-N mode.