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A 0.72 nW, 1 Sample/s Fully Integrated pH Sensor with 65.8 LSB/pH Sensitivity 一个0.72 nW, 1个样品/s全集成pH传感器，65.8 LSB/pH灵敏度
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/vlsicircuits18222.2020.9163023
Yihan Zhang, F. Cardoso, K. Shepard
{"title":"A 0.72 nW, 1 Sample/s Fully Integrated pH Sensor with 65.8 LSB/pH Sensitivity","authors":"Yihan Zhang, F. Cardoso, K. Shepard","doi":"10.1109/vlsicircuits18222.2020.9163023","DOIUrl":"https://doi.org/10.1109/vlsicircuits18222.2020.9163023","url":null,"abstract":"This paper presents a 0.85 mm2 fully integrated pH sensor IC utilizing an ion sensitive field effect transistor (ISFET) and reference field effect transistor (REFET) pair in which the native foundry passivation layer is used as an ion sensitive layer. The pH sensor has 10 bit resolution with 65.8 LSB/pH sensitivity, while consuming only 0.72 nW at 1 sample/s, improving an overall figure of merit (FoM) that accounts for power, sampling frequency, and sensitivity by > 4000×.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116267934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm 基于1MS/s到1GS/s ringamp的流水线ADC，具有全动态参考调节和随机片上范围背景监测
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162788
B. Hershberg, N. Markulić, J. Lagos, E. Martens, D. Dermit, J. Craninckx
{"title":"A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm","authors":"B. Hershberg, N. Markulić, J. Lagos, E. Martens, D. Dermit, J. Craninckx","doi":"10.1109/VLSICircuits18222.2020.9162788","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162788","url":null,"abstract":"This paper presents an 11 bit fully dynamic pipelined ADC with an integrated reference buffer that consumes only 8% of total power. It operates from 1MS/s to 1GS/s and maintains 59.5dB SNDR and 14fJ/conv-step FoMW across this range. Furthermore, a small circuit is introduced that provides background reconstruction of amplifier settling behavior.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133207773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 1200×1200 8-Edges/Vertex FPGA-Based Motion-Planning Accelerator for Dual-Arm-Robot Manipulation Systems 基于1200×1200 8边/顶点fpga的双臂机器人操作系统运动规划加速器
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/vlsicircuits18222.2020.9162951
Atsutake Kosuge, T. Oshima
{"title":"A 1200×1200 8-Edges/Vertex FPGA-Based Motion-Planning Accelerator for Dual-Arm-Robot Manipulation Systems","authors":"Atsutake Kosuge, T. Oshima","doi":"10.1109/vlsicircuits18222.2020.9162951","DOIUrl":"https://doi.org/10.1109/vlsicircuits18222.2020.9162951","url":null,"abstract":"An SoC-FPGA-based motion-planning accelerator operating on a graph with >10M edges is presented for the first time for dual-am-robot manipulation systems. The proposed modified A∗ algorithm with minimized memory access time, is further accelerated by extensive parallel computation and dynamic reconfigurations. The proposed accelerator has been verified by measurement result showing overall motion-planning time of 0.5 seconds, which is only 1/100 of the one by conventional algorithm on embedded CPU, while preserving accuracy.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134081158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Probabilistic Self-Annealing Compute Fabric Based on 560 Hexagonally Coupled Ring Oscillators for Solving Combinatorial Optimization Problems 一种基于560个六方耦合环振子的概率自退火计算结构用于求解组合优化问题
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162869
Ibrahim Ahmed, Po-Wei Chiu, C. Kim
{"title":"A Probabilistic Self-Annealing Compute Fabric Based on 560 Hexagonally Coupled Ring Oscillators for Solving Combinatorial Optimization Problems","authors":"Ibrahim Ahmed, Po-Wei Chiu, C. Kim","doi":"10.1109/VLSICircuits18222.2020.9162869","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162869","url":null,"abstract":"NP-hard combinatorial optimization problems (COPs) are very expensive to solve with traditional computers. COPs can be mapped to a coupled spin network where the ground state of the system is the solution. We propose a scalable truly coupled CMOS oscillator-based integrated system mimicking a spin network to solve COPs in hardware. Our simple latch-based coupling design finds solutions of max-cut problems with 85%–100% accuracy 104-106 times faster than commercial software running on a CPU.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116538574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
An 8-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor with 60 Mel-Frequency Energy Features Enabling 95% Speech Recognition Accuracy 具有60 mel频率能量特征的8元频率选择声学波束形成器和比特流特征提取器，可实现95%的语音识别精度
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/vlsicircuits18222.2020.9162783
Seungjong Lee, Taewook Kang, John Bell, M. Haghighat, Alberto J. Martinez, M. Flynn
{"title":"An 8-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor with 60 Mel-Frequency Energy Features Enabling 95% Speech Recognition Accuracy","authors":"Seungjong Lee, Taewook Kang, John Bell, M. Haghighat, Alberto J. Martinez, M. Flynn","doi":"10.1109/vlsicircuits18222.2020.9162783","DOIUrl":"https://doi.org/10.1109/vlsicircuits18222.2020.9162783","url":null,"abstract":"A synergistic approach to beamforming and feature extraction, reduces processing complexity and die area, and delivers the high SNR required for reliable speech recognition. The 1.1mm2 IC combines frequency-selective bitstream beamforming, bitstream Mel frequency-band feature extraction, and an array of continuous-time sigma-delta modulators (SDMs) without area/power-intensive decimation. When coupled with a DNN, the prototype achieves 95.3% accuracy in recognizing spoken words from the Tensorflow dataset.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115735314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications 边缘机器人和增强现实应用中用于高效3D场景重建的10nm CMOS光线投射加速器
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9163067
Monodeep Kar, A. Agarwal, S. Hsu, D. Moloney, Gregory K. Chen, Raghavan Kumar, H. Sumbul, Phil C. Knag, M. Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, R. Krishnamurthy, V. De
{"title":"A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications","authors":"Monodeep Kar, A. Agarwal, S. Hsu, D. Moloney, Gregory K. Chen, Raghavan Kumar, H. Sumbul, Phil C. Knag, M. Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, R. Krishnamurthy, V. De","doi":"10.1109/VLSICircuits18222.2020.9163067","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9163067","url":null,"abstract":"A ray-casting accelerator in 10nm CMOS simultaneously casts multiple rays in spatial proximity to exploit voxel data-locality, featuring a near-memory search for voxel address overlaps and opportunistic approximate trilinear interpolation for energy savings. Measurements demonstrate ray-casting of 320×240 depth images with an average latency of 23.2ms/frame, while consuming 32.7pJ energy per ray-step and achieving a maximum energy-efficiency of 115.3 giga raysteps/W.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130146742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM 全重量片DNN加速器在22纳米ULL具有24×1 Mb eRRAM
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/vlsicircuits18222.2020.9162811
Zhehong Wang, Ziyun Li, Li Xu, Qing Dong, Chin-I Su, W. Chu, George Tsou, Y. Chih, T. Chang, D. Sylvester, Hun-Seok Kim, D. Blaauw
{"title":"An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM","authors":"Zhehong Wang, Ziyun Li, Li Xu, Qing Dong, Chin-I Su, W. Chu, George Tsou, Y. Chih, T. Chang, D. Sylvester, Hun-Seok Kim, D. Blaauw","doi":"10.1109/vlsicircuits18222.2020.9162811","DOIUrl":"https://doi.org/10.1109/vlsicircuits18222.2020.9162811","url":null,"abstract":"We present a DNN accelerator in 22nm ULL CMOS featuring 24×1 Mb embedded RRAM. The accelerator, composed of 4 PEs and 512 MACs, achieves 0.96 TOPS/W at 120 MHz with 0.8 V VDD. Each PE contains 6 RRAM macros, equipped with a dynamic clamping offset-canceling sense amplifier that offers sub-μA current input offset.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122478828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Portable NMR System with 50-kHz IF, 10-us Dead Time, and Frequency Tracking 具有50 khz中频，10 us死区时间和频率跟踪的便携式核磁共振系统
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/vlsicircuits18222.2020.9163029
Sungjin Hong, Nan Sun
{"title":"A Portable NMR System with 50-kHz IF, 10-us Dead Time, and Frequency Tracking","authors":"Sungjin Hong, Nan Sun","doi":"10.1109/vlsicircuits18222.2020.9163029","DOIUrl":"https://doi.org/10.1109/vlsicircuits18222.2020.9163029","url":null,"abstract":"This paper presents a portable nuclear magnetic resonance (NMR) system with significantly enhanced capabilities. Unlike prior works that use the same clock frequency for TX excitation and RX LO, this work uses two separate frequencies with a 50-kHz intermediate frequency (IF) that break the tradeoff between on-resonance excitation and 1/f-noise & offset suppression. It also proposes an accurate but low-cost method to ensure two clocks' phase coherence, which is necessary for NMR time-domain averaging. Moreover, this work addresses the critical limitation of long RX dead time (∼1ms) in prior works. By dynamically adjusting high-pass corner frequencies of IF filters and amplifiers, it shortens the dead time by 100 times to only 10us. Additionally, an automatic frequency tracking technique is devised to address the magnetic field drift problem. This work also reports the highest integration level achieved for an NMR transceiver, with on-chip ADC and DLL. Various measurements have been performed for system validation.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121286133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 4.3fJ/Conversion-Step 6440μm2 All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse 4.3fJ/转换步长6440μm2的高效电荷复用全动态电容-数字转换器
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162817
Haoming Xin, Kevin Pelzers, P. Baltus, E. Cantatore, P. Harpe
{"title":"A 4.3fJ/Conversion-Step 6440μm2 All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse","authors":"Haoming Xin, Kevin Pelzers, P. Baltus, E. Cantatore, P. Harpe","doi":"10.1109/VLSICircuits18222.2020.9162817","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162817","url":null,"abstract":"An ultra-low power all-dynamic capacitance-to-digital converter (CDC) that exploits a novel charge reuse technique is proposed, achieving a FoM as low as 4.3fJ/conv-step, which is >3× better than the state-of-the-art. It supports an inherent scaling of power vs. speed with a minimum power of only 44pW and a compact chip area of 6440μm2.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121192953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR 用于下一代固态激光雷达的2D-SPAD阵列和读出AFE
2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI: 10.1109/VLSICircuits18222.2020.9162831
T. Ta, H. Kubota, K. Kokubun, Toshiki Sugimoto, Masatoshi Hirono, M. Sengoku, Hisaaki Katagiri, H. Okuni, Satoshi Kondo, Shinichi Ohtsuka, H. Kwon, K. Sasaki, Yutaka Ota, Kazuhiro Suzuki, K. Kimura, K. Yoshioka, A. Sai, Nobu Matsumoto
{"title":"A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR","authors":"T. Ta, H. Kubota, K. Kokubun, Toshiki Sugimoto, Masatoshi Hirono, M. Sengoku, Hisaaki Katagiri, H. Okuni, Satoshi Kondo, Shinichi Ohtsuka, H. Kwon, K. Sasaki, Yutaka Ota, Kazuhiro Suzuki, K. Kimura, K. Yoshioka, A. Sai, Nobu Matsumoto","doi":"10.1109/VLSICircuits18222.2020.9162831","DOIUrl":"https://doi.org/10.1109/VLSICircuits18222.2020.9162831","url":null,"abstract":"This paper introduces several key RX techniques to realize a 200m-range and low-cost high-pixel-resolution solid-state LiDAR for autonomous self-driving systems. In-Sensor Scanning 2D-SPAD array can remove the mechanical mirror and improve the pixel-resolution by implying short dead time active-quenching SPADs. For ToF calculating SoC, we adopt the world first dual-data converter (DDC) which consolidates the functions of ADC and TDC into a single circuitry, achieving the acquisition of both high-precision time/voltage data from a single input. Such innovations lead us to 200m-range 300×80-pixel solid-state LiDAR RX under 70klux solar radiation.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125521873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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