A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm

Abstract

This paper presents an 11 bit fully dynamic pipelined ADC with an integrated reference buffer that consumes only 8% of total power. It operates from 1MS/s to 1GS/s and maintains 59.5dB SNDR and 14fJ/conv-step FoMW across this range. Furthermore, a small circuit is introduced that provides background reconstruction of amplifier settling behavior.