4.3fJ/转换步长6440μm2的高效电荷复用全动态电容-数字转换器

2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI:10.1109/VLSICircuits18222.2020.9162817

Haoming Xin, Kevin Pelzers, P. Baltus, E. Cantatore, P. Harpe

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引用次数: 8

摘要

提出了一种超低功耗全动态电容-数字转换器(CDC)，该转换器利用一种新颖的电荷重用技术，实现了低至4.3fJ/ v-step的FoM，比目前的技术好3倍以上。它支持功率与速度的固有缩放，最小功率仅为44pW，芯片面积紧凑，为6440μm2。

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A 4.3fJ/Conversion-Step 6440μm2 All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse

An ultra-low power all-dynamic capacitance-to-digital converter (CDC) that exploits a novel charge reuse technique is proposed, achieving a FoM as low as 4.3fJ/conv-step, which is >3× better than the state-of-the-art. It supports an inherent scaling of power vs. speed with a minimum power of only 44pW and a compact chip area of 6440μm2.

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2020 IEEE Symposium on VLSI Circuits

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