全重量片DNN加速器在22纳米ULL具有24×1 Mb eRRAM

2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI:10.1109/vlsicircuits18222.2020.9162811

Zhehong Wang, Ziyun Li, Li Xu, Qing Dong, Chin-I Su, W. Chu, George Tsou, Y. Chih, T. Chang, D. Sylvester, Hun-Seok Kim, D. Blaauw

{"title":"全重量片DNN加速器在22纳米ULL具有24×1 Mb eRRAM","authors":"Zhehong Wang, Ziyun Li, Li Xu, Qing Dong, Chin-I Su, W. Chu, George Tsou, Y. Chih, T. Chang, D. Sylvester, Hun-Seok Kim, D. Blaauw","doi":"10.1109/vlsicircuits18222.2020.9162811","DOIUrl":null,"url":null,"abstract":"We present a DNN accelerator in 22nm ULL CMOS featuring 24×1 Mb embedded RRAM. The accelerator, composed of 4 PEs and 512 MACs, achieves 0.96 TOPS/W at 120 MHz with 0.8 V VDD. Each PE contains 6 RRAM macros, equipped with a dynamic clamping offset-canceling sense amplifier that offers sub-μA current input offset.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM\",\"authors\":\"Zhehong Wang, Ziyun Li, Li Xu, Qing Dong, Chin-I Su, W. Chu, George Tsou, Y. Chih, T. Chang, D. Sylvester, Hun-Seok Kim, D. Blaauw\",\"doi\":\"10.1109/vlsicircuits18222.2020.9162811\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a DNN accelerator in 22nm ULL CMOS featuring 24×1 Mb embedded RRAM. The accelerator, composed of 4 PEs and 512 MACs, achieves 0.96 TOPS/W at 120 MHz with 0.8 V VDD. Each PE contains 6 RRAM macros, equipped with a dynamic clamping offset-canceling sense amplifier that offers sub-μA current input offset.\",\"PeriodicalId\":252787,\"journal\":{\"name\":\"2020 IEEE Symposium on VLSI Circuits\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vlsicircuits18222.2020.9162811\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsicircuits18222.2020.9162811","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

我们提出了一个DNN加速器在22nm的ULL CMOS具有24×1 Mb嵌入式RRAM。该加速器由4个pe和512个mac组成，在120 MHz和0.8 V VDD下达到0.96 TOPS/W。每个PE包含6个RRAM宏，配备一个动态箝位偏移抵消感测放大器，提供亚μ a电流输入偏移。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM

We present a DNN accelerator in 22nm ULL CMOS featuring 24×1 Mb embedded RRAM. The accelerator, composed of 4 PEs and 512 MACs, achieves 0.96 TOPS/W at 120 MHz with 0.8 V VDD. Each PE contains 6 RRAM macros, equipped with a dynamic clamping offset-canceling sense amplifier that offers sub-μA current input offset.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2020 IEEE Symposium on VLSI Circuits

自引率

0.00%

发文量