A 1 GS/s Reconfigurable BW 2nd-Order Noise-Shaping Hybrid Voltage-Time Two-Step ADC Achieving 170.9 dB FoMS

Abstract

This paper presents a reconfigurable BW 2nd-order noise-shaping (NS) hybrid voltage-time ADC based on the two-step ADC structure. Composed by a SAR ADC in the 1st stage and a time-based-converter (TBC) in the 2nd stage, with a reconfigurable passive filter, it realizes a 2nd-order NS while simultaneously maintaining a simple and high-speed operation. Due to the delay introduced by the inter-stage residue amplifier (RA), one NS order is inherently provided by the pipelined architecture. Fabricated in 28 nm CMOS, the prototype chip operates at 1 GS/s while consuming 2.3 mW at 1 V. At an OSR of 4, the SNDR is 63.58 dB leading to a 170.9 dB FoMS. Thanks to the reconfigurable filter, the ADC is able to achieve 163.5 dB and 171.6 dB FoMs at OSR of 2 and 6, respectively.