一个紧凑的14 GS/s 8位开关电容DAC在16纳米FinFET CMOS

2020 IEEE Symposium on VLSI Circuits Pub Date : 2020-06-01 DOI:10.1109/VLSICircuits18222.2020.9162776

P. Caragiulo, O. E. Mattia, A. Arbabian, B. Murmann

{"title":"一个紧凑的14 GS/s 8位开关电容DAC在16纳米FinFET CMOS","authors":"P. Caragiulo, O. E. Mattia, A. Arbabian, B. Murmann","doi":"10.1109/VLSICircuits18222.2020.9162776","DOIUrl":null,"url":null,"abstract":"This paper presents a compact DAC for digital-intensive transmitter architectures. To minimize area and to leverage the strengths of FinFET CMOS, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad switched capacitors. The 14 GS/s 8-bit design occupies only 0.011 mm2 and supports up to 0.32 Vpp signal swing across its differential 100 Ω load. It achieves IM3 < −45.3 dBc across the first Nyquist zone while consuming 50 mW from a single 0.8 V supply.","PeriodicalId":252787,"journal":{"name":"2020 IEEE Symposium on VLSI Circuits","volume":"97 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A Compact 14 GS/s 8-Bit Switched-Capacitor DAC in 16 nm FinFET CMOS\",\"authors\":\"P. Caragiulo, O. E. Mattia, A. Arbabian, B. Murmann\",\"doi\":\"10.1109/VLSICircuits18222.2020.9162776\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a compact DAC for digital-intensive transmitter architectures. To minimize area and to leverage the strengths of FinFET CMOS, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad switched capacitors. The 14 GS/s 8-bit design occupies only 0.011 mm2 and supports up to 0.32 Vpp signal swing across its differential 100 Ω load. It achieves IM3 < −45.3 dBc across the first Nyquist zone while consuming 50 mW from a single 0.8 V supply.\",\"PeriodicalId\":252787,\"journal\":{\"name\":\"2020 IEEE Symposium on VLSI Circuits\",\"volume\":\"97 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSICircuits18222.2020.9162776\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSICircuits18222.2020.9162776","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

本文提出了一种用于数字密集型发射机架构的紧凑型DAC。为了最小化面积并利用FinFET CMOS的优势，该实现与传统的电流转向方法不同，主要由逆变器和亚飞法拉开关电容器组成。14 GS/s 8位设计仅占用0.011 mm2，在其差分100 Ω负载上支持高达0.32 Vpp的信号摆幅。它在第一个奈奎斯特区实现IM3 < - 45.3 dBc，同时从单个0.8 V电源消耗50 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A Compact 14 GS/s 8-Bit Switched-Capacitor DAC in 16 nm FinFET CMOS

This paper presents a compact DAC for digital-intensive transmitter architectures. To minimize area and to leverage the strengths of FinFET CMOS, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad switched capacitors. The 14 GS/s 8-bit design occupies only 0.011 mm2 and supports up to 0.32 Vpp signal swing across its differential 100 Ω load. It achieves IM3 < −45.3 dBc across the first Nyquist zone while consuming 50 mW from a single 0.8 V supply.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2020 IEEE Symposium on VLSI Circuits

自引率

0.00%

发文量