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2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)最新文献

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Voltage choosing of OBIRCH for finger metal structure 手指金属结构用OBIRCH的电压选择
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564235
LinMeng Yang, Bobby Chan, G. Qian, Li-Lung Lai, Rui Fang
{"title":"Voltage choosing of OBIRCH for finger metal structure","authors":"LinMeng Yang, Bobby Chan, G. Qian, Li-Lung Lai, Rui Fang","doi":"10.1109/IPFA.2016.7564235","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564235","url":null,"abstract":"As a tool to localize defects, OBIRCH is widely used in solving the problem of FAB low yield issue. Choosing a proper voltage is critical for the effective working of OBIRCH. This paper proposes a method to analyze the critical voltage of OBIRCH used to the finger metal structure. Based on the measurement data including current and voltage, an empirical formula has been simulated to calculate Sigma (current comparative difference). Three cases show proper voltage arises while the Sigma had the maximum value. It is proved that the method proposed is effective to choose a correct voltage for the working of OBIRCH.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115296067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimized trapezoid FIB sample preparation method for dielectric nanocharacterization 电介质纳米表征的优化梯形FIB样品制备方法
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564333
C. Guedj, E. Martinez
{"title":"Optimized trapezoid FIB sample preparation method for dielectric nanocharacterization","authors":"C. Guedj, E. Martinez","doi":"10.1109/IPFA.2016.7564333","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564333","url":null,"abstract":"A novel FIB sample preparation for advanced BEOL, FEOL and beyond CMOS dielectric reliability is presented. The simultaneous milling of the two sides of the lamella with trapezoidal dual milling patterns results in a thin (~30 nm) TEM sample with minimum implantation and damage. The resulting geometry is strain-symmetrized and free from curtain effect. The optimum crystal quality is assessed by Auger and EDX spectrometry, equal orientation fringes, strain mapping and quantitative analysis of HRTEM images. The complex dielectric permittivity of advanced dielectric stacks is properly mapped by energy loss spectroscopy only when this preparation method is used. The nanostructure and conduction properties of a nanofilament inside hafnia are henceforward measured, which provide a direct insight into the physics of resistive memory (ReRAM) cells or high-K gate dielectric defectivity at the nanometric scale.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126444438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Chemical analysis of semiconductor devices using TEM energy-dispersive X-ray spectroscopy (EDS) and electron energy-loss spectroscopy (EELS) 利用TEM能量色散x射线能谱(EDS)和电子能量损失能谱(EELS)对半导体器件进行化学分析
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564254
Jie Zhu, Y. Shen, S. Zhao
{"title":"Chemical analysis of semiconductor devices using TEM energy-dispersive X-ray spectroscopy (EDS) and electron energy-loss spectroscopy (EELS)","authors":"Jie Zhu, Y. Shen, S. Zhao","doi":"10.1109/IPFA.2016.7564254","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564254","url":null,"abstract":"In this paper, we discussed the challenges of chemical analysis using TEM energy-dispersive X-ray spectroscopy (EDS) and electron-energy loss spectroscopy (EELS) for semiconductor devices. In the first case study, we showed that EDS peak overlapping and Bremsstrahlung background may cause false “signals” during defect element analysis. The problem can be solved using the EDS full quantification analysis instead of the conventional raw intensity integration method. In the second example, we described how to enhance the contrast of defect mapping using EELS spectrum imaging or jump ratio method. In the third example, EELS oxygen K-edge chemical shift and energy-loss near edge structure (ELNES) were used to characterize oxidized Ta thin film deposited on SiO2. In this case, EDS technique failed because of poor energy resolution and electron beam spreading effect. In the last case, plasmons in the EELS low-loss region were used to identify different nickel silicide phases in a thin film. Other techniques such as selected area diffraction (SAD) and nano-beam diffraction (NBD) are limited by the area-selection aperture size or specimen tilting. It is also shown that non-linear least square Gaussian fitting can be used to resolve the spectrum recorded at the interface.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116951774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Application of MOSFET characteristic measurement for electrical isolation of open defect on device level in failure analysis MOSFET特性测量在器件级开路缺陷电隔离分析中的应用
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564282
Li Tian, Xuejian Qian, Gaojie Wen, Jinrong Song, Hao Zhang, Diwei Fan, Dong Wang
{"title":"Application of MOSFET characteristic measurement for electrical isolation of open defect on device level in failure analysis","authors":"Li Tian, Xuejian Qian, Gaojie Wen, Jinrong Song, Hao Zhang, Diwei Fan, Dong Wang","doi":"10.1109/IPFA.2016.7564282","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564282","url":null,"abstract":"With multi-metal layers and scaling down we occurred many difficulties in FA(Failure Analysis). Due to coverage of metal layers many signals couldn't be measured with planting probing pad in electrical analysis. And usually EMMI (Emission Microscope)or OBIRCH (Optical Beam Induced Resistor Change) analysis didn't reveal defect directly for open defect. So, it was difficult to isolate open failure and confirm its location on device level. In recent years some novel technologies or studies were developed for open defect, for example forcing method, triangular wave, logic time sequence analysis and so on. But we still couldn't make sure open location on device level with these methods. In this paper we proposed one novel and effective method for isolating open issue on device level. The main idea was that measuring MOSFET characteristics to confirm its status to isolate open defect. The two characteristics of MOSFET included Ids-Vds and Ids-Vgs curves which were applied to find open issue in two real cases respectively. In these two cases abnormal IdS-Vds and IdS-Vgs characteristics were detected respectively, and then we could deduce open issue based on measurement result. After PFA (Physical Failure Analysis), the defect was found to cause abnormal Ids. Thus, we believed the advantages of MOSFET characteristic measurement method were novel, effective and low cost. It was beneficial to our FA for open defect on device level in electrical failure isolation.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123967885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Decapsulation of copper wire devices with high Tg mold compound using microwave induced plasma 微波诱导等离子体解封高Tg模化合物铜线器件
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564332
J. Tang, J. Wang, T. Tan, M. Endo, K. Ng, L. Lee, C. Beenakker
{"title":"Decapsulation of copper wire devices with high Tg mold compound using microwave induced plasma","authors":"J. Tang, J. Wang, T. Tan, M. Endo, K. Ng, L. Lee, C. Beenakker","doi":"10.1109/IPFA.2016.7564332","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564332","url":null,"abstract":"Epoxy mold compound with high Tg is used for high temperature applications such as automotive. However, downside of using high Tg EMC is the difficulty in preserving copper bond wires during acid decapsulation. The use of silver plated leadframes makes stitch bond exposure even more difficult as acid and conventional plasma etching easily attacks silver. A new decapsulation process is developed based on Microwave Induced Plasma etching to handle high Tg plastic copper wire packages.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125902767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-throughput sample preparation method for Cu pillar FCQFN 铜柱FCQFN的高通量制样方法
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564261
Ke-Ying Lin, Wenjing Wang, Sharon Chen
{"title":"High-throughput sample preparation method for Cu pillar FCQFN","authors":"Ke-Ying Lin, Wenjing Wang, Sharon Chen","doi":"10.1109/IPFA.2016.7564261","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564261","url":null,"abstract":"We present a fast and high-throughput sample preparation method for FA (failure analysis) of Cu pillar FCQFN package. Our method facilitates simultaneous decapsulation of multiple devices, and with reduced number of package decapsulation steps. Further, throughput-time (TPT) for sample preparation is reduced from 90 min to 30 min.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125772597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Field-dependent degradation mechanisms in GaN-based HEMTs 氮化镓基hemt的场依赖降解机制
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564252
M. Meneghini, G. Meneghesso, I. Rossetto, J. Bartholomeus, F. Rampazzo, C. de Santi, D. Bisi, E. Zanoni
{"title":"Field-dependent degradation mechanisms in GaN-based HEMTs","authors":"M. Meneghini, G. Meneghesso, I. Rossetto, J. Bartholomeus, F. Rampazzo, C. de Santi, D. Bisi, E. Zanoni","doi":"10.1109/IPFA.2016.7564252","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564252","url":null,"abstract":"GaN-based transistors are emerging as almost ideal devices for application in the power conversion field; however, several factors still limit their performance and reliability. This paper reviews the most common field-dependent degradation mechanisms in GaN-based power transistors. Based on the analysis of commercially-available devices we present data on: (i) the recoverable increase in on-resistance due to the exposure to high drain bias, in the off-state; (ii) the permanent degradation of 650 V transistors submitted to off-state step stress with increasing drain bias. The results obtained on commercially-available devices are critically compared to previous papers on the topic, to provide an extensive overview of the physical origin of the degradation.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"30 21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125737519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
BTI lifetime reliability of planar MOSFET versus FinFET for 16 nm technology node 16nm技术节点平面MOSFET与FinFET的BTI寿命可靠性
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564296
M. Mahmoud, N. Soin
{"title":"BTI lifetime reliability of planar MOSFET versus FinFET for 16 nm technology node","authors":"M. Mahmoud, N. Soin","doi":"10.1109/IPFA.2016.7564296","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564296","url":null,"abstract":"As FinFET pushes to replace planar MOSFET, concern rises about its reliability. This research detects the more robust technology against BTI aging degradation, through investigating its effect at the device level: using an adequate BTI Reaction Diffusion model, and at the circuit level for 16nm nodes. FinFET proves to be more robust, as its delay due to BTI is lower by 26% compared to planar MOSFET.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132229351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Asymmetric low temperature bonding structure using ultra-thin buffer layer technique for 3D integration 非对称低温键合结构采用超薄缓冲层技术进行三维集成
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564307
Hao-Wen Liang, Ting-Yang Yu, Yao-Jen Chang, Kuan-Neng Chen
{"title":"Asymmetric low temperature bonding structure using ultra-thin buffer layer technique for 3D integration","authors":"Hao-Wen Liang, Ting-Yang Yu, Yao-Jen Chang, Kuan-Neng Chen","doi":"10.1109/IPFA.2016.7564307","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564307","url":null,"abstract":"Wafer-level Sn/In-Cu bonding structure with Ni ultra-thin buffer layer is investigated to achieve a reduction in solder thickness, bonding temperature and duration. Furthermore, the asymmetric bonding structure is able to separate the manufacturing process of solder and electrical isolation layer. It is a promising approach for the application on hybrid bonding of three-dimensional integration.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123154341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Barrier height reconfiguration of graphene/ZnO:N barristor using ferroelectric polymer 铁电聚合物对石墨烯/ZnO:N电阻器势垒高度的重构
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2016-07-18 DOI: 10.1109/IPFA.2016.7564293
K. Seo, J. H. Yang, J. Yoo, H. Hwang, K. Chang, C. H. Shim, S. K. Lee, C. Cho, Y. Kim, B. H. Lee
{"title":"Barrier height reconfiguration of graphene/ZnO:N barristor using ferroelectric polymer","authors":"K. Seo, J. H. Yang, J. Yoo, H. Hwang, K. Chang, C. H. Shim, S. K. Lee, C. Cho, Y. Kim, B. H. Lee","doi":"10.1109/IPFA.2016.7564293","DOIUrl":"https://doi.org/10.1109/IPFA.2016.7564293","url":null,"abstract":"We demonstrate and explain the operation of PVDF-TrFE/graphene/ZnO:N barristor using electrostatic force microscopy (EFM) poling system. The device was successfully reconfigured using a ferroelectric polymer, PVDF-TrFE. ~103 of device current modulation were achieved. And, it will be very useful for dynamically reconfigurable logic, memory and logic-memory hybrid device applications.","PeriodicalId":206237,"journal":{"name":"2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124560242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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